Makiko Ito, Mitsuru Tomono, Yi Ge et al. · 2013
We have developed a vector coprocessor for a wireless baseband SoC for mobile devices using processor description language. The design of the vector coprocessor is highly-complex and it requires a lot of design time and costs with a conventional design flow. To address this problem, we developed an architecture design flow with an untimed model and a performance estimator. We achieved 4.5 times better design efficiency compared to a conventional implementation design flow with a timed model. As a result, we were able to reduce design and optimization time dramatically.
Cited by 1
Tetsuo Hironaka, Takashi Hashimoto, Keizo Okazaki et al. · 1992
This paper presents the benchmark results on a vector-processor prototype based on the MSFV (multithreaded streaming/FIFO vector) architecture. The MSFV architecture is single-chip oriented, and thus its main object is to save the off-chip memory bandwidth by exploiting the register bandwidth instead. The register bandwidth is exploited by the synergism of FIFO register, chaining, streaming, and multithreading. This paper tries to identify the strength and weakness of those architectural features. The results for basic vector operations and Livermore Fortran Kernels are reported in terms of normalized FLOPC (floating-point operations per clock cycle) and compared to previously-reported results on the Cray X-MP, Y-MP, Fujitsu VP-200, Hitachi S-810/20, NEC SX-2, and SX-3. These comparisons show that, for many basic vector operations, the execution rate of the MSFV prototype results in worst due to its saving the memory bandwidth. However, for Livermore Fortran Kernels, the MSFV prototype results in worst due to its saving the memory bandwidth. However, for Livermore Fortran Kernels, the MSFV prototype outperforms the VP-200 by 2.11 times (geometric mean) and one processor of the X-MP by 1.22 times (geometric mean) in terms of FLOPC. Also, it is 0.67 times (geometric mean) faster than the S-810/20, and 0.76 times (geometric mean) faster than the SX-2. The paper concludes that the MSFV architecture is successful in saving the memory bandwidth.
Cited by 2
Atsushi Inoue, Akira Maeda · Parallel Computing · 1988
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Ruth Christiana Huang · 2013
Designing Anti-Islanding Detection Using the Synchrophasor Vector Processor Ruth Huang The need for distributed generation (DG) has become more and more popular because of the adverse effects of fossil fuels and the fear of running out of fossil fuels. By having DG, there are less transmission losses, voltage support, controllability of the system, decreased costs in transmission and distribution, power quality improvement, energy efficiency, and reduced reserve margin. The adverse effects of DG are voltage flicker, harmonics, and islanding. Islanding occurs when the DG continues to energize the power system when the main utility is disconnected. Detecting islanding is important for personnel safety, speedy restoration, and equipment protection. This paper describes the different islanding methods currently used and the benefits of combining two passive islanding detection methods, under/over voltage detection and voltage phase jump detection methods, using the synchrophasor vector processor (SVP).
Cited by 0Open access
Vahid Sadeghian · TSpace · 2012
VecTor© is a suite of computer programs developed for nonlinear finite element analysis of reinforced concrete. A graphics-based pre-processor (FormWorks) was developed for 2D concrete membrane structures, greatly contributing to the software’s utility and success. However, modeling other types of structures is a time consuming process, requiring manual definition of the finite element mesh, loads and analysis parameters in standard text files. A user-friendly pre-processor is required for the entire suite of programs if they are to be of greater use to design engineers. The purpose of this study is to develop an updated version of FormWorks, FormWorks 3.5, which is more user-friendly and compatible with the improvements made in VecTor2 over the past ten years. In addition, an extended version of FormWorks, FormWorks-Plus, will be created for the remaining VecTor programs with a wide range of viewing features, and facilities for specification of node coordinates, elements, loads and material properties.
Cited by 4Open access
Michael R. Feldman, Clark C. Guest · 1989
High speed computation of the product of a vector and a matrix is desirable for problems in neural networks, signal processing, artificial intelligence and many other applications. If the number of elements in the vector is N, and the number in the matrix is N 2 , then a serial computer requires a time which grows at least as N 2 to complete the computation. Many processing elements (PE's) can be combined to form a processor array in order to decrease the computation time. Electrically connected processor arrays are effective for locally connected parallel processing networks[1], A linear mesh can be used to perform the multiplication in time proportional to N [2], However to compute the product in shorter time, more complicated schemes with non local connection lengths are required. For such networks, the interconnections themselves are often responsible for a large percentage of the computation time, power dissipation and silicon area. Optically interconnected processor arrays can be employed to reduce this communication bottleneck. Previous work has shown that optical interconnections have advantages in terms of power dissipation and communication bandwidth for sufficiently long interconnection paths[3], and in terms of area for sufficiently complex connection networks[4].
Cited by 0
Nakazawa Kisaburo, Hiromitsu Kawabe · 1992
In this paper, we present a new architecture for highspeed pseudo vector processor based on a superscalar pipeline. Without using cache memory, the proposed architecture is able to overcome penalty of memory access latency by introducing register windows with register preloading and pipelined memory. One outstanding feature of the proposed architecture is that it is upward compatible with existing scalar architectures. Performance evaluation of the proposed architecture using the Livermore Loop Kernels shows over 6 times higher performance than a usual superscalar processor and 1.2 times higher performance than a hypothetical extended model with cache prefetching technique with a memory access latency of 20 CPU clock cycles. List vectors are also effectively handled in a similar architecture. 1. Introduction Motivation Over the past several years, technological and architectural advances have realized dramatic improvements in microprocessor performance with peak performances becoming...
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Nikolay Dikarev, B. M. Shabanov, Aleksandr Shmelëv · Program systems theory and applications · 2018
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Cited by 2Open access
Lin, X Xintan · TU/e Research Portal (Eindhoven University of Technology) · 2012
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Kawabata, S. · Mendeley Data · 2019
Abstract A program package, VBASES, a supercomputer version of multi-dimensional integration package BASES, has been developed. It was applied to the calculation of cross section for the radiative Bhabha process. The execution time of the integration was shortened by a factor of 80 in comparison with that by a scalar computer. Title of program: VBASES Catalogue Id: ABBU_v1_0 Nature of problem In high energy physics the numerical integration package is used to obtain the cross section for the physical process. When the physical process is complicated, the integrand may become a very long Fortran source code. In such a case, the integration itself requires too much CPU time for practical use. Versions of this program held in the CPC repository in Mendeley Data ABBU_v1_0; VBASES; 10.1016/0010-4655(88)90201-9 This program has been imported from the CPC Program Library held at Queen's University Belfast (1969-2019)
Cited by 0Open access
H.T. Pierick, D. Teuling · International Conference on Consumer Electronics · 2005
A vector processor' is presented which generates correction signals for medium and high performance color monitors. It processes deflection (x,y) vectors in e.g. (RBx, RBy), (Gx, Cy) as well as other areas such as brightness uniformity. Alignment is in a 3x3 point or quasi 5x5 point correction matrix. In a typical application the convergence errors for 3x3 correction are halved, and for a quasi 5x5 correction reduced to one third. Non-interactive alignment is achieved by quadrant selection. The vector processor contains two identical channels.
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Yeyong Pang, Shaojun Wang, Peng Yu et al. · Chinese Journal of Electronics · 2017
FPGA based soft vector processing accelerators are used frequently to perform highly parallel data processing tasks. Since they are not able to implement complex control manipulations using software, most FPGA systems now incorporate either a soft processor or hard processor. A FPGA based AXI bus compatible vector accelerator architecture is proposed which utilises fully pipelined and heterogeneous ALU for performance, and microcoding is employed for reusability. The design is tested with several design examples in four different lane configurations. Compared with Central processing unit (CPU), Digital signal processor (DSP), Altera C2H tool and OpenCL SDK implementations, the vector processor improves on execution time and energy consumption by factors of up to 6.6 and 6.4 respectively.
Cited by 0Open access
D. H. Rudy · NASA Technical Reports Server (NASA) · 1987
Two-dimensional subsonic laminar compressible base flow has been studied using numerical solutions of the time-dependent Navier-Stokes equations. These solutions were obtained using an explicit finite-difference scheme which is highly efficient on a vector processor. The organization of the code for a CDC CYBER-205 computer is described. Solutions were obtained for Mach 0.4 and 0.6 flows past a slender blunt-based model at moderately high Reynolds numbers. The flow in the wake is unsteady with periodic shedding of vortices from the trailing edge. The computed shedding frequency was found to increase with increasing Reynolds number.
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Ingemar Kinnmark, William G. Gray · Developments in water science · 1988
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V. Naveen Chander, Kuruvilla Varghese · 2022
Edge computing is the key to unlocking the power of deep neural networks on edge devices. However, deploying power-hungry deep neural network inference on resource-constrained and power-limited devices poses serious challenges in delivering real-time performance. With the advent of RISC-V Vector extension, there has been a renewed interest in vector processors to exploit data-parallel workloads. General purpose processors featuring vector coprocessors are riddled with complex control mechanisms such as instruction schedulers, operand queues, and scoreboards which have largely inhibited their presence in the realm of low-power microcontrollers. This work features a systolic array based vector unit that is closely integrated into the pipeline of a 32-bit, in-order, single-issue RISC-V scalar core that runs at 50 MHz. The robustness of neural networks coupled with the flexibility offered by the RISC-V Vector extension instruction set is used to significantly reduce several architectural complexities of the vector unit. The vector processor is implemented on Xilinx Virtex 7 (XC7VX485T) FPGA. Benchmarking the RISC-V Vector processor shows a speedup of up to $40.7\times$ over the scalar RISC-V core on image recognition tasks at the cost of $1.2\times$ power consumption and $1.8\times$ hardware resources. The soft core vector processor also compares well with similar processors that use data-level parallelism.
Cited by 16
Cao Yu, Zhi Gang Han, Wei Xiao et al. · 2020
With the continuous improvement of people’s safety awareness, infrared products as human motion detection technology have been widely used in the field of security. In order to better apply infrared products to life, improving the performance of infrared products and reducing the cost of products has become the main goal. According to the signal collected by Pyroelectric infrared (PIR) sensor, this paper establishes a database model. According to the data collected, Kalman filter is used to preprocess the data. The validity of the data after preprocessing is judged by the algorithm. The experimental results show that the accuracy of the model can reach 97% by using a support vector machine (SVM) algorithm incorporated with Fast Fourier Transform (FFT). According to the above algorithm flow, a real-time intellectual property (IP) core is designed by using hardware description language, after establishing the data processing algorithm. The interface design, timing design and function design of the IP core are designed. The IP core can be connected to the microcontroller unit (MCU) as an independent peripheral to form a PIR special processor, which can detect the distance of 15 m in real time.
Cited by 1
M. Bellos, Dimitris Nikolos · Lecture notes in computer science · 2005
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Kangkang Chen, Huayou Su, Chaorun Liu et al. · Lecture notes in computer science · 2024
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Shun’ichi Torii, Keiji Kojima, Yasusi Kanada et al. · 2003
The problems of utilizing an extended vector processor called IDP (Integrated Database Processor) for nonnumerical processing are discussed. IDP has highly pipelined merge and search vector facilities in addition to conventional vector facilities. This extended vector processor can be utilized not only for primitive relational operations but also for the following applications: (1) complex relational query using multiple indexes; (2) multiway merge/sort utility, and (3) generation and test processing. Vectorization methods and performance improvements are described and analyzed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 8
C. Kim, C. Shen · 1980
The problem of obtaining smoothed estimates of function values, particularly their derivatives, from a finite set of inaccurate measurements is considered. A recursive two-dimensional vector processor is introduced as an approximation to the nonrecursive constrained least-squares estimation. Here, piecewise bicubic Hermite polynomials are extensively used as approximating functions, and the smoothing integral is converted to a discrete quadratic form. This makes it possible to convert the problem of fitting an approximating function to one of estimating the function values and derivatives at the nodes.
Cited by 1