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About 6,839 papers for “Processor array”

Phased array antenna beamforming using optical processor

L. Anderson, F. Boldissar, D. C. D. Chang · NASA Technical Reports Server (NASA) · 1991

The feasibility of optical processor based beamforming for microwave array antennas is investigated. The primary focus is on systems utilizing the 20/30 GHz communications band and a transmit configuration exclusively to serve this band. A mathematical model is developed for computation of candidate design configurations. The model is capable of determination of the necessary design parameters required for spatial aspects of the microwave 'footprint' (beam) formation. Computed example beams transmitted from geosynchronous orbit are presented to demonstrate network capabilities. The effect of the processor on the output microwave signal to noise quality at the antenna interface is also considered.

Cited by 0

Benchmarking an associative processor array for vision

Pout, M., Duller, A.W.G. · Digital library of Zielona Gora (University of Zielona Góra) · 1993

The DARPA Image Understanding Benchmarks are used to measure the suitability of the GLiTCH associative processor architecture for a range of vision related tasks. hl particular the tasks of edge detection, connected component labelling and the Hough transform are discussed in some detail. Results are then presented for two different array sizes for all of the image understanding tasks.

Cited by 1Open access

Structured Design for an LPC Array Processor

Glen J. Culler · 1978

Abstract : The architecture of an array processor that is tailored to the requirements of LPC analysis and synthesis is presented. Interim results in the development of a structured design system are also given. Keywords include LPC analysis; LPC synthesis; Array processor; Logical design; Logical modules; Structured design; and Computer architecture.

Cited by 0

Standardized parallel sorting on SIMD array processor

Tianzhen Wang, Li Zhou, Qin Xiozhen · 2002

We present the standardized parallel sorting algorithm. Instead of the most basic CCI (compare and conditional interchange) operation in traditional sorting algorithms, this algorithm compares sorting data with a standard value sequence simultaneously and synchronously on an SIMD array processor. The algorithm possesses three significant advantages. First, the running time T is independent of the problem size, T=0(1). The second attractive feature of the algorithm is that it is not necessary to build a communication network between PEs. Finally, no bottleneck occurs in output. We have implemented the algorithm in an SIMD array processor that is designed by our research group. The experiment verifies all the theoretical predictions. For these merits the algorithm is of significance in both theory and practice.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 0

Systolic Processor Array For Recognition Of Spectra

Edward T. Chow, John C. Peterson · 1995

Spectral signatures of materials detected and identified quickly. Spectral Analysis Systolic Processor Array (SPA2) relatively inexpensive and satisfies need to analyze large, complex volume of multispectral data generated by imaging spectrometers to extract desired information: computational performance needed to do this in real time exceeds that of current supercomputers. Locates highly similar segments or contiguous subsegments in two different spectra at time. Compares sampled spectra from instruments with data base of spectral signatures of known materials. Computes and reports scores that express degrees of similarity between sampled and data-base spectra.

Cited by 0

Model-based towed array processor: Experimental results

Edmund J. Sullivan, Dieter Brecht, Leif Persson · The Journal of the Acoustical Society of America · 2000

Results of a towed array bearing estimation experiment using a model-based processor are presented. The experiment took place in the southern Baltic using an Atlas towed array. The towship was the Swedish corvette Gavle. Results for the case of a 121-Hz source are presented. The towship ran in a straight line, past the source, where the distance of closest approach was 500 m. A short overview of the model-based approach, which is based on a state space formulation using a Kalman estimator, will be presented. By formulating the problem in state space form, it is possible to include sophisticated models in the processor. This, in effect, is a self-consistent means of including a priori information into the processing. It will be shown that the inclusion of the array’s forward motion provides significant improvement in performance over the conventional processor in terms of the variance of the estimate. The improvement in performance arises from the bearing information contained in the forward motion of the array. This information obtains, from the time scale, change in the signal or, in the narrrow-band case, the Doppler. The experimental results clearly show the improvement over the conventional processor.

Cited by 0

Testing of analog neural array-processor chips

W.-J. Hsu, B.J. Sheu, S. Gowda · 2002

A systematic approach to test analog array-processor neural chips is presented. Unique testing problems for analog neural chips are described and effective solutions are discussed. Based on the hierarchical methodology, testing of analog array-processor neural chips can be systematically addressed. The test results for programmable analog neural chips fabricated by a 2- mu m CMOS process are presented. These chips contain 25 neurons and 1600 synapses.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 5

MICOM Experimental Array Radar Digital Signal Processor.

Lancaster,James F. · Defense Technical Information Center (DTIC) · 1973

A detailed description of the digital signal processor used with the MICOM Experimental Array Radar (EAR) is presented in this report. The EAR system is a C-band, monopulse, phased array radar designed to perform the functions of sector search and target track for air defense applications. The signal processor samples range returns in real time at a 5-MHz rate to provide various processing functions for the radar. The basic functions provided by the signal processor are: clutter rejection, signal-to-noise improvement, threshold detection, and information for range and angle tracking. (Author)

Cited by 0

Programmable inner-product enhanced associative processor array

Subhash C. Balam, K. Hariharakrishnan, Dan Schonfeld · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2004

Associative Processors have become popular because of their ability to perform parallel operations in massive scale. The use of Associative Processors especially for MPEG4/H.263 video coding was found to have low power consumption. However they lack the ability to perform computationally intensive block transforms. The paper discusses requirements for video processing and shows how Associative Processors are more suited for video coding than RISC architectures. We highlight the various drawbacks of using Associative Processors for video coding and propose a new Distributed Arithmetic based enhancement to the architecture that provides greater flexibility in the implementation of video coding algorithms. These modifications help in faster computation of DCT and simulations of the proposed enhancement show that MPEG 4 simple profile encoder can be implemented in less than 10 MIPS.

Cited by 0

A CORDIC based programmable DXT processor array

V. Anuradha, V. Visvanathan · 2002

A CORDIC based processor array which can be programmed by switch setting to compute the Discrete Hartley, Cosine or Sine Transforms or their inverses is described. Through a novel formulation of the transform computations in the CORDIC framework, N-point transforms are mapped on to a linear array of /spl lsqb/N/2/spl rsqb/+1 CORDIC processors with minimal control overhead to incorporate the programmability.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 1

A massively parallel diagonal-fold array processor

G.G. Pechanek, J.G. Delgado-Frias, S. Vassiliadis · 2002

Image processing for multimedia workstations is a computationally intensive task typically requiring special purpose hardware, for example a nearest neighbor mesh parallel machine organization. One type of nearest neighbor mesh computer consists of a K /spl times/ K square array of Processor Elements (PEs) where each PE is connected to the North, South, East, and West PEs only. In a torus configuration, there are a total of 2K/sup 2/ PE interfaces. Under the assumption of SIMD operation with unidirectional message and data transfers between the PEs, it is possible to reconfigure the array by placing the symmetric PEs together and share the north-south wires with the east-west wires, thereby reducing the wiring complexity in half, i.e. K/sup 2/ PE interfaces without affecting performance. This new machine organization is termed the Diagonal-Fold Mesh Array Processor, providing equivalent performance to a nearest neighbor mesh with half the wiring complexity for unidirectional data transferring algorithms.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 5

Processor array design with FPGA area constraint

Joseph Fernando, Jack Jean · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1999

Digital signal processing algorithms with multiple shift-invariant dependence graphs (DGs) can be mapped to field programmable gate array hardware in many different types of systolic processor arrays. Because of the finite amount of hardware resources, the problem is to use a "right" amount of hardware in a specific configuration so to maximize the processing speed. In this paper, the problem of finding the right processor array configuration is formulated as a constrained optimization problem where the cost function includes not only the cost of individual processor arrays but also the cost of interfacing circuits. Three heuristic algorithms are presented for the optimization problem. Among them, both the Lth axial neighbor algorithm and the simulated annealing algorithm produce good results on a test case. Simulation results on the test case also indicate that the initial configuration is important in getting a good configuration for both algorithms. The Lth axial neighbor algorithm has the extra advantage of requiring less amount of performance tuning.

Cited by 1

Resolving Power of an Optimum Array Processor

Henry Cox · The Journal of the Acoustical Society of America · 1973

The classical concept of resolution consists of recognizing that an observed effect is due to two separate sources. The resolving power of an optimum array processor which is based on the inversion of the signal-plus-noise cross-spectral matrix is examined. Exact conditions are presented for resolution of closely spaced sources by an optimum beamformer. These results are applied to a line array and compared with the resolution capability of a conventional beamformer. For equal strength sources it is found, for example, that an output signal-to-noise ratio of about 47 dB is required to achieve a resolving power with an optimum processor which is ten times that given by the classical Rayleigh limit. Conditions are also presented for the resolution of two sources of unequal strength. It is shown that two closely spaced sources of unequal strength will be resolved by the optimum beamformer if the strength of the weaker source is slightly larger than that required for resolution of two equi-strength sources in the same geometric configuration.

Cited by 1