Singanaboina, Srinivas Yadav · Civil War Book Review · 2024
The exponential growth in computational power and the increasing demand for high-performance applications have driven the need for greater parallel efficiency. Over the years, the number of cores in consumer-level CPUs and high-performance computing (HPC) systems has grown significantly. In response, numerous parallel programming li- braries have been developed. Each of these libraries offers unique mechanisms to enhance parallel performance. In this paper, we investigate the performance of five such paral- lel programming backends: C++ std::execution::par, OpenMP, TBB, Taskflow, and HPX. We evaluate these libraries using two sets of benchmarks. The first set focuses on standard C++ STL algorithms, including for_each, reduce, scan, and sort. The second set involves real-world mini-applications, such as Black-Scholes, Mandelbrot, LULESH, and miniBUDE. Our findings provide insights into how to further optimize HPX algo- rithms and how to fine-tune performance by adopting the best practices from various par- allel backends. This analysis helps us understand the relative performance of HPX among other libraries and suggests areas for future improvement.
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Murugadoss Venu, B. P. Dileep, H.L. Raghavendra et al. · 2024
Adders are the most fundamental element of any digital system, and they are one of the most often utilized digital components in digital integrated circuit design. The Central Processing Unit (CPU) is the primary processing unit of any device capable of carrying out computations. The Arithmetic and Logical Unit (ALU) is a crucial component of the CPU, with adders being the primary and indispensable component. Arithmetic operation efficiency is vital in today's digital systems, and adder architectural selection has a big effect on total performance. This -paper compares various 8-bit, 16-bit, and 32-bit digital parallel adders: carry select adder, ripple carry adder and carry skip adder, or the delay, power consumption, and area. The design is written in verilog HDL and simulated in xillinx vivado. In terms of propagation delay, power efficiency, and resource usage, this study demonstrates the distinct advantages and trade-offs of RCA, CSA, and CSLA. It provides insightful information for choosing the best adder design based on application-specific needs.
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Boschetti, G, Gasparetto, Alessandro, Zanotto, V. · Institutional Research Information System (University of Udine) · 2015
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Felix Wolf, Felix Freitag, Bernd Mohr et al. · 2006
A powerful and widely-used method for analyzing the performance behavior of parallel programs is event tracing. When an application is traced, performance-relevant events, such as entering functions or sending messages, are recorded at run-time and analyzed post-mortem to identify and potentially remove performance prob-lems. While event tracing enables the detection of performance problems at a high level of detail, growing trace-file size often constrains its scalability on large-scale systems and complicates management, analysis, and visualization of trace data. In this article, we survey current approaches to handle large traces and classify them accord-ing to the primary issues they address and the primary benefits they offer.
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A. N. Pears, M.L. Ojczyk · 2007
Previous research indicates that geometric hashing can provide a reliable and transformation independent representation of a target. The characterisation of a target object is obtained by establishing a vector basis relative to a number of interest points unique to the target. The representation is invariant under both affine and geometric transformations of the target interest points. A previous paper[4] discusses the complexity measures associated with task division and target image processing using geometric hashing. These measures were used to determine the areas which most benefit from implementation in hardware; and an architecture design for a high speed, hardware assisted, geometric hashing approach to target recognition was described. To confirm the performance of a parallel hardware approach to target recognition based on geometric hashing a complete component level simulation of the proposed hardware has been developed using OBJECTSIM. OBJECTSIM [5] is an object oriented a...
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P. M. Abhilash, A. Chandrashekhar · Indian Journal of Science and Technology · 2018
In this paper the performance analysis of one of the most commonly used parallel manipulator is been discussed. Performance analysis explains the difference performance factors of parallel manipulators like Condition number, Manipulability index, Transmission index, Minimum singular value, Stiffness index etc. In this Paper we are going to deal with indices like Transmission index, stiffness index and condition number. Three different structures are considered for the analysis. In each structure, for the entire dexterous workspace best postures of the manipulators are identified based on the performance measures. Keywords: Condition Number, Parallel Manipulators, Performance Analysis, Stiffness Index, Transmission Index
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Guangkui Xu, S.D. Silverstein, R. Roy et al. · 1991
Most high-resolution algorithms for sensor array processing require an eigendecomposition which is difficult to implement in parallel and costs at least O(M/sup 3/) multiplications for an M*M matrix, corresponding to M sensors. Recently, S.D. Silverstein et al, (1991) presented a subband parallel scheme, which reduced the computation time from O(M/sup 3/) to O(L/sup 3/), where L(<M) is the subband length or the beamspace dimension. However, the potential problem is that a uniform linear array commonly used in direction finding loses its displacement invariance structure after the beamspace transformation. Thus, the DOA estimation may be more computationally intensive since the computationally efficient ESPRIT algorithm cannot be applied directly. The authors show a way of restoring the lost structure, which results in a new beamspace ESPRIT algorithm. The asymptotic performance analysis and simulation results of the beamspace ESPRIT method are presented.<<ETX>>
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Tonglei Cheng, Yichi Shen · International Journal of Communication Systems · 1997
Asynchronous transfer mode (ATM) switches can be constructed by connecting multiple banyan networks in parallel. To utilize the capacity of the parallel banyan networks fully, it is crucial to allow up to L cells from each input to be switched, and up to L cells to be received by each output simultaneously, where L is the total number of parallel banyan networks. This is possible if the switch operates in L overlapping phases and one banyan network is used to switch cells in each phase. Although a couple of such designs have been proposed and simulated, there is a lack of suitable models for such switches to be analysed mathematically. In this paper, two approximate analyses of a parallel banyan ATM switch are described. A comparison of the analytical and simulation results show that the analyses give reasonably accurate results. © 1997 by John Wiley & Sons, Ltd.
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Lucas Leandro Nesi, Vinícius Garcia Pinto, Marcelo Cogo Miletto et al. · HAL (Le Centre pour la Communication Scientifique Directe) · 2020
High-performance computing (HPC) applications enable the solution of compute-intensive problems in feasible time. Among many HPC paradigms, task-based programming has gathered community attention in recent years. This paradigm enables constructing an HPC application using a more declarative approach, structuring it in a direct acyclic graph (DAG). The performance evaluation of these applications is as hard as in any other programming paradigm. Understanding how to analyze these applications, employing the DAG and runtime metrics, presents opportunities to improve its performance. This article describes the StarVZ R-package available on CRAN for performance analysis of task-based applications. StarVZ enables transforms runtime trace data into different vi-sualizations of the application behavior. An analyst can understand their applications' performance limitations and compare multiple executions. StarVZ has been successfully applied to several study-cases, showing its applicability in a number of scenarios.
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Rare & Special e-Zone (The Hong Kong University of Science and Technology) · 2003
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Geimer, M. · JuSER (Forschungszentrum Jülich) · 2007
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Bradley, Jeremy, Knottenbelt, William, Hayden, Richard Alexander · OpenGrey (Institut de l'Information Scientifique et Technique) · 2011
The accurate performance analysis of large-scale computer and communication systems is directly inhibited by an exponential growth in the state-space of the underlying Markovian performance model. This is particularly true when considering massively-parallel architectures such as cloud or grid computing infrastructures. Nevertheless, an ability to extract quantitative performance measures such as passage-time distributions from performance models of these systems is critical for providers of these services. Indeed, without such an ability, they remain unable to offer realistic end-to-end service level agreements (SLAs) which they can have any confidence of honouring. Additionally, this must be possible in a short enough period of time to allow many different parameter combinations in a complex system to be tested. If we can achieve this rapid performance analysis goal, it will enable service providers and engineers to determine the cost-optimal behaviour which satisfies the SLAs. In this thesis, we develop a scalable performance analysis framework for the grouped PEPA stochastic process algebra. Our approach is based on the approximation of key model quantities such as means and variances by tractable systems of ordinary differential equations (ODEs). Crucially, the size of these systems of ODEs is independent of the number of interacting entities within the model, making these analysis techniques extremely scalable. The reliability of our approach is directly supported by convergence results and, in some cases, explicit error bounds. We focus on extracting passage-time measures from performance models since these are very commonly the language in which a service level agreement is phrased. We design scalable analysis techniques which can handle passages defined both in terms of entire component populations as well as individual or tagged members of a large population. A precise and straightforward specification of a passage-time service level agreement is as important to the performance engineering process as its evaluation. This is especially true of large and complex models of industrial-scale systems. To address this, we introduce the unified stochastic probe framework. Unified stochastic probes are used to generate a model augmentation which exposes explicitly the SLA measure of interest to the analysis toolkit. In this thesis, we deploy these probes to define many detailed and derived performance measures that can be automatically and directly analysed using rapid ODE techniques. In this way, we tackle applicable problems at many levels of the performance engineering process: from specification and model representation to efficient and scalable analysis.
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Gagandeep Singh, Acet Manawala Amritsar, Chhailadeep Kaur et al. · 2012
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Ertel, W., Muenchen Technische Univ. (Germany). Inst. fuer Informatik · OpenGrey (Institut de l'Information Scientifique et Technique) · 1991
With random competition we propose a method for parallelizing arbitrary theorem provers. We can prove high efficiency (compared with other parallel theorem provers) of random competition on highly parallel architectures with thousands of processors. This method is suited for all kinds of distributed memory architectures, particularly for large networks of high performance workstations since no communication between the processors is necessary during run-time. On a set of examples we show the performance of random competition applied to the model elimination theorem prover SETHEO. Besides the speedup results for random competition our theoretical analysis gives fruitful insight in the interrelation between search-tree structure, run-time distribution and parallel performance of OR-parallel search in general.
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Boris Sedov, Alexey Syschikov, Yuriy Sheynin et al. · SHILAP Revista de lepidopterología · 2015
During the embedded system development an estimation of software performance on different hardware is needed. Estimation of the expected acceleration of program execution on various numbers of processors, estimation of computation space etc. Such estimations, as other aspects of performance analysis complex, should help with different problems that arise at the intersection of software and hardware parts. For example, selection of the most successful hardware platform from available options for current program solution or modernization of the program for better resource use of given hardware platform and achieve best performance. In the paper tool of static analysis is considered. It is a part of the complex of program performance analysis in integrated development environment VIPE for perspective multicore embedded systems.
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Laura Grigori, Xiaoye Sherry Li · eScholarship (California Digital Library) · 2004
We investigate performance characteristics for the LU factorization of large matrices with various sparsity patterns. We consider supernodal right-looking parallel factorization on a bi-dimensional grid of processors, making use of static pivoting. We develop a performance model and we validate it using the implementation in SuperLU_DIST, the real matrices and the IBM Power3 machine at NERSC. We use this model to obtain performance bounds on parallel computers, to perform scalability analysis and to identify performance bottlenecks. We also discuss the role of load balance and data distribution in this approach.
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Szebenyi, Z. · JuSER (Forschungszentrum Jülich) · 2011
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Jan Lemeire, Erik Dirkx · 2007
This paper proposes a generalised model of parallel performance. Our research investigates how far a generalised approach can obtain the same detailed results as current instantiated analysis of specific parallel algorithms. Performance is decomposed into the different overhead sources, that are expressed analytically and we showed how to separate the dependency of the algorithm and the system. We present a new method to overcome reported problems on measurability of overheads and this detailed analysis reveals `hidden&apos; sources of blocking overhead, due to communication or extra computation. The presented approach can lead to an automated experimental analysis, in order to support performance prediction, straight forward development of parallel programs, and can be used in partitioning and load balancing algorithms. Therefore, it is focussed on the programmers viewpoint of parallel processing.
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Alexey Lastovetsky, Ravi Reddy · 2004
The paper presents an approach to performance analysis of heterogeneous parallel algorithms. As a typical heterogeneous parallel algorithm is just a modification of some homogeneous one, the idea is to compare the heterogeneous algorithm with its homogeneous prototype, and to assess the heterogeneous modification rather than analyse the algorithm as an isolated entity. A criterion of optimality of heterogeneous parallel algorithms is suggested. A parallel algorithm of matrix multiplication on heterogeneous clusters is used to illustrate the proposed approach. Ó 2004 Elsevier B.V. All rights reserved.
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Sotirios G. Ziavras · 2007
Interprocessor connection networks with very good topological properties are often impossible to build because of their prohibitively high wire complexity. Such a network is the generalized hypercube (GH) that supports full-connectivity of all its nodes in each dimension. We present here the class of HOW interprocessor connections which are capable of lower complexity than GHs, comparable performance, and better scalability. We analyze the hardware cost of HOWs, present communications algorithms for 2-D HOWs, and carry out performance comparisons with binary hypercubes and GHs. Keywords: Parallel computer, interconnection network, cost analysis, communications operations. 1 Introduction Developing low-complexity, high-bisection bandwidth, and low-latency networks to interconnect processors (PEs) in MPP systems is a Herculean task. Several message passing interconnection networks have been proposed for parallel computers [1]. To support scalability, current approaches most often use b...
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