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About 10,000 papers for “Bit array”

Sparse Array Optimization Based on Bit-by-Bit Search Algorithm

Yuanyuan Jia, Yifeng Wu, Jinwan Zhang · 2024

This paper presents a sparse array optimization method based on the bit-by-bit search strategy, specifically aimed at reducing the peak side-lobe level of the array. The algorithm initiates with a random global exploration, followed by a localized refinement through sequential bit-wise optimization, ingeniously integrating greedy strategies with principles of dynamic programming. This approach effectively circumvents local optima while accelerating convergence to the globally optimal configuration. Experimental results under comparable conditions demonstrate that, compared to existing methods such as Genetic Algorithms and Artificial Bee Colony algorithms, this strategy achieves significant enhancements in array performance while concurrently reducing computational complexity.

Cited by 0

Bit-Array-Based Alternatives to HyperLogLog

Svante Janson, Jérémie Lumbroso, Robert Sedgewick · Uppsala University Publications (Uppsala University) · 2024

We present a family of algorithms for the problem of estimating the number of distinct items in an input stream that are simple to implement and are appropriate for practical applications. Our algorithms are a logical extension of the series of algorithms developed by Flajolet and his coauthors starting in 1983 that culminated in the widely used HyperLogLog algorithm. These algorithms divide the input stream into M substreams and lead to a time-accuracy tradeoff where a constant number of bits per substream are saved to achieve a relative accuracy proportional to 1/√M. Our algorithms use just one or two bits per substream. Their effectiveness is demonstrated by a proof of approximate normality, with explicit expressions for standard errors that inform parameter settings and allow proper quantitative comparisons with other methods. Hypotheses about performance are validated through experiments using a realistic input stream, with the conclusion that our algorithms are more accurate than HyperLogLog when using the same amount of memory, and they use two-thirds as much memory as HyperLogLog to achieve a given accuracy.

Cited by 0Open access

Bit-Array-Based Alternatives to HyperLogLog

Jérémie Lumbroso · arXiv (Cornell University) · 2018

Naively storing a counter up to value n would require Ω(log n) bits of memory. Nelson and Yu [Jelani Nelson and Huacheng Yu, 2022], following work of Morris [Robert H. Morris, 1978], showed that if the query answers need only be (1+ε)-approximate with probability at least 1 - δ, then O(log log n + log log(1/δ) + log(1/ε)) bits suffice, and in fact this bound is tight. Morris' original motivation for studying this problem though, as well as modern applications, require not only maintaining one counter, but rather k counters for k large. This motivates the following question: for k large, can k counters be simultaneously maintained using asymptotically less memory than k times the cost of an individual counter? That is to say, does this problem benefit from an improved amortized space complexity bound? We answer this question in the negative. Specifically, we prove a lower bound for nearly the full range of parameters showing that, in terms of memory usage, there is no asymptotic benefit possible via amortization when storing multiple counters. Our main proof utilizes a certain notion of "information cost" recently introduced by Braverman, Garg and Woodruff [Mark Braverman et al., 2020] to prove lower bounds for streaming algorithms.

Cited by 0Open access

Bit-array-based alternatives to HyperLogLog

Svante Janson, Jérémie Lumbroso, Robert Sedgewick · Theoretical Computer Science · 2025

We present a family of algorithms for the problem of estimating the number of distinct items in an input stream that are simple to implement and are appropriate for practical applications. Our algorithms are a logical extension of the series of algorithms developed by Flajolet and his coauthors starting in 1983 that culminated in the widely used HyperLogLog algorithm. These algorithms divide the input stream into M substreams and lead to a time-accuracy tradeoff where a small number of bits per substream are saved to achieve a relative accuracy proportional to 1 / M . Our algorithms use just one or two bits per substream. Their effectiveness is demonstrated by a proof of approximate normality, with explicit expressions for standard errors that inform parameter settings and allow proper quantitative comparisons with other methods. Performance hypotheses are validated through experiments using a realistic input stream, with the general conclusion that our algorithms are significantly more accurate than HyperLogLog when using the same amount of memory, and they use significantly less memory than HyperLogLog to achieve a given accuracy. • Efficient algorithms for estimating the number of distinct items in a data stream. • Explicit characterization of the distribution of reported values. • Detailed fair comparisons with other algorithms in the literature. • Sufficient detail to enable development of real-world implementations.

Cited by 0Open access

Optimised bit level systolic array for convolution

J.V. McCanny, J.G. McWhirter, K. Wood · IEE Proceedings F Communications Radar and Signal Processing · 1984

A bit level systolic array for computing the convolution operation is described. The circuit in question is highly regular and ideally suited to VLSI chip design. It is also optimised in the sense that all the cells contribute to the computation on each clock cycle. This makes the array almost four times more efficient than one which was previously described.

Cited by 14

Programming languages for bit-serial array machines

Dennis Mancl · 1981

Many high-level languages have been created or are under development for large nearest-neighbor connected multiprocessors, such as the ILLIAC IV, the ICL DAP, and the Goddard-Goodyear MPP. These higher-level languages are intended to make these machines easier to program. Programming languages for these array machines should be designed to fit a particular applications area. This means that the language can be powerful and efficient, yet small and easy to learn. The basic data types of the language can be mapped to the machine structure. The operations of the language can be implemented to run as efficiently as possible. A programming language for numerical linear algebra problems has been implemented that generates code for the MPP. The basic data types of the language are vector, matrix, and banded matrix. The operations include matrix-vector multiplication, Jordan exchange, and orthogonal transformations.

Cited by 2

Virtual MIMO Array by One-Bit Transmission

Xinzhu Chen, Lei Huang, Qiang Li et al. · 2024

This paper concentrates on an array radar system that transmits coherent signals with one-bit DAC and receives by one-bit filtering. Such an architecture realizes a virtual MIMO array radar without sending orthogonal signals. It benefits not only in transmitting in a simplified circuit at full power but also cutting down computational burden in receive, thereby making the radar suitable especially on small-size platforms, e.g. car and UAV. First, the signal model is developed under a monochromatic assumption. The one-bit signal correlation is derived by expanding the well-known arcsin law using Fourier Transform. Based on that, the correlation matrix is formulated as an infinite sum of rank-one matrix and verified to be full-rank, thereby remaining the transmit DOFs. Second, simulation on system performance is provided to compare between the phased array, the proposed array and an ideal MIMO array, validating that by converting and transmitting the correlated signal in one bit, it achieves nearly good beamforming and DOA estimation resolution as the ideal MIMO array radar.

Cited by 0

Implicit array bounds checking on 64-bit architectures

Chris Bentley, Scott A. Watterson, David K. Lowenthal et al. · ACM Transactions on Architecture and Code Optimization · 2006

Several programming languages guarantee that array subscripts are checked to ensure they are within the bounds of the array. While this guarantee improves the correctness and security of array-based code, it adds overhead to array references. This has been an obstacle to using higher-level languages, such as Java, for high-performance parallel computing, where the language specification requires that all array accesses must be checked to ensure they are within bounds. This is because, in practice, array-bounds checking in scientific applications may increase execution time by more than a factor of 2. Previous research has explored optimizations to statically eliminate bounds checks, but the dynamic nature of many scientific codes makes this difficult or impossible. Our approach is, instead, to create a compiler and operating system infrastructure that does not generate explicit bounds checks. It instead places arrays inside of Index Confinement Regions (ICRs), which are large, isolated, mostly unmapped virtual memory regions. Any array reference outside of its bounds will cause a protection violation; this provides implicit bounds checking. Our results show that when applying this infrastructure to high-performance computing programs written in Java, the overhead of bounds checking relative to a program with no bounds checks is reduced from an average of 63% to an average of 9%.

Cited by 0Open access

Multibit convolution using a bit level systolic array

J.G. McWhirter, D. Wood, K. Wood et al. · IEEE Transactions on Circuits and Systems · 1985

A novel design for multibit convolver circuits is described. The circuits take the form of systolic arrays of simple one-bit processor and memory cells, with the result that they can operate at very high data rates and should be easy to implement using VLSI technology. An efficient method for handling two's complement data within the array is described and the relative advantages of this convolver design compared with more conventional circuits is discussed.

Cited by 17

Feedback bit allocation in distributed antenna array systems

Shuai ZHANG, Peng PAN, Cui WANG · SHILAP Revista de lepidopterología · 2020

In a frequency division duplex communication system,precoding at the base station usually requires terminal feedback channel state information.In a distributed array system,the channel conditions between the terminal and different access nodes in the cell are different because multiple access nodes are arranged at different locations in the cell.When the resources for feedback channel state information are limited,the allocation method of feedback bit needs to be optimized to improve the overall performance of the system.In a multi-user distributed array system,an access node selection method based on distance threshold was adopted.Based on this method,the quantization characteristics of the random vector quantization codebook and the Taylor expansion method were used to derive the system quantization capacity loss,and then an approximate expression was given.Based on this expression,a feedback bit allocation method was proposed.Compared with other allocation methods,the method of this paper was more universal because it did not limit the number of access nodes selected by the user.The simulation results show that the strategy proposed is superior to the traditional equal-bit allocation scheme and can obtain better performance when the feedback resources are limited.

Cited by 0Open access

A bit-level systolic array for median filter

Chang Lu, J.-H. Lin · IEEE Transactions on Signal Processing · 1992

A bit-level systolic array for median filters based on the majority of the bit strings of input samples is presented. The majority function can be implemented by a 1-b odd/even transposition network, which is regular and can be designed easily. If each input sample is represented by r bits, the systolic array contains r processor elements and requires time complexity O(N+n+r-1) for a stream of N samples with window size n in a one-dimensional median filter.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 31

Power analysis of bit interleaving 9T SRAM array

S. Karthika, N. M. Sivamangai · 2016

Soft error issue is major concern in SRAM array. It can be overcome if the array is constructed in bit interleaving architecture. Hence in this paper, an analysis of bit interleaving SRAM array to overcome soft error using 9T SRAM cell has been made. It shows that 9T SRAM array with bit interleaving architecture has less power and has good stability when compared to shared word line architecture using 6T SRAM cell. Area, Power and SNM has been compared for 6T SRAM and 9T SRAM. Results indicates that 9T SRAM cell shows power reduction of 75.89 % when compared to conventional 6T SRAM cell with trade - off of 25.98 % increase in area. The 9T SRAM cell also has 63.03 % improvement in SNM than 6T SRAM cell.

Cited by 3