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About 455 papers for “CABAC”
The Hawaii Sugar Planters Association Filipino Laborer files include data on over 100,000 migrants to Hawaii from 1906-1949. The original collection consists of individual cards, shipping manifests, log books, and associated administrative records.
Cited by 0
Alcăt. M. Fotescu, Ed. îngr. De E. Harconiţa · Zenodo (CERN European Organization for Nuclear Research) · 2019
Personalitate marcantă a Universităţii, în viziunea dr. hab. Gh. Popa, întruchipează un om al profesionalismului, al managementului, al salahoriei (în sensul bun al cuvîntului), al calmului, al bunei dispoziţii, al povestirii, avînd felul său inconfundabil de a fi şi norocul de a fi permanent în posesia tinereţii mature. Biobibliografia îl prezintă pe dl Valeriu Cabac în ipostazele de profesor universitar, cercetător ştiinţific, specialist manager, coleg de breaslă.
Cited by 0Open access
Alcăt. M. Fotescu, Ed. îngr. De E. Harconiţa · Zenodo (CERN European Organization for Nuclear Research) · 2019
Personalitate marcantă a Universităţii, în viziunea dr. hab. Gh. Popa, întruchipează un om al profesionalismului, al managementului, al salahoriei (în sensul bun al cuvîntului), al calmului, al bunei dispoziţii, al povestirii, avînd felul său inconfundabil de a fi şi norocul de a fi permanent în posesia tinereţii mature. Biobibliografia îl prezintă pe dl Valeriu Cabac în ipostazele de profesor universitar, cercetător ştiinţific, specialist manager, coleg de breaslă.
Cited by 0Open access
P. Zhang · Electronics Letters · 2008
A novel high-performance decoding architecture for H.264 context-based adaptive binary arithmetic coding (CABAC) is presented, where several efficient techniques such as speculative decoding, table-based calculation, logic balancing, mathematic reordering and optimal retiming are adopted to reduce the critical timing path. Simulation and implementation results show that the architecture can achieve a fixed decoding rate of up to 247.5 Mbin/s, which is 67% faster than conventional architectures.
Cited by 13
Xiaohua Tian, Thinh M. Le, Yong Lian · Signals and communication technology · 2010
Cited by 0
Salma Ben Jamaa, Michel Kieffer, Pierre Duhamel · 2010
Cited by 0
Ryuichi Hattori, Kazuo Sugimoto, Yasutaka Itani et al. · 2012
In this paper, improved bypass mode for CABAC called pass through mode is proposed. The bypass mode stands for a special coding process in CABAC to be used for encoding a symbol having equal probability. The proposed scheme realizes complexity reduction of the bypass mode in decoder without any loss of compression performance. We implemented the proposed scheme into test model software that is used for HEVC standardization process to evaluate its performance. Our experimental result shows that the run-time of the bypass mode process in decoder is reduced by about 60 %.
Cited by 1
Philipp Habermann · DepositOnce · 2020
Video applications have emerged in various fields of our everyday life. They have continuously enhanced the user experience in entertainment and communication services. All this would not have been possible without the evolution of video compression standards and computer architectures over the last decades. Modern video codecs employ sophisticated algorithms to transform raw video data to an intermediate representation consisting of syntax elements, which allows enormous compression rates before reconstructing the video with minimal objective quality losses compared to the original video. Modern computer architectures lay the foundation for these computationally intensive tasks. They provide multiple cores and specialized vector architectures to exploit the massive amount of parallelism that can be found in video applications. Customized hardware solutions follow the same principles. Parallel processing is essential to satisfy real-time performance constraints while optimizing energy efficiency, the latter being the most important design goal for mobile devices. One of the main tasks in modern video compression standards implements a highly sequential algorithm and lacks data-level parallelism in contrast to all other compute-intensive tasks: Context-based Adaptive Binary Arithmetic Coding (CABAC). It is the entropy coding module in the state-of-the-art High Efficiency Video Coding (HEVC) standard and also its successor Versatile Video Coding. Its purpose is the compression and decompression of the intermediate video representation by exploiting statistical properties, thus achieving minimal bitrates. CABAC is one of the main throughput bottlenecks in video coding applications due to the limited parallelization opportunities, especially for high-quality videos. Close-distance control and data dependencies make CABAC even more challenging to implement with modern computer architectures. This thesis addresses the critical CABAC decoding throughput bottleneck by proposing multiple approaches to uncover new parallelization opportunities and to improve the performance with architectural optimizations. First of all, we quantitatively verify the severity of the CABAC decoding throughput bottleneck by evaluating the HEVC decoding performance for various workloads using a representative selection of state-of-the-art computer architectures. The results show that even the most powerful processors cannot provide real-time performance for several high-quality workloads. The profiling results clearly show that CABAC decoding is the main reason for that in most cases. Wavefront Parallel Processing (WPP) is a well-established high-level parallelization technique used in video coding and other applications. It can lead to a high degree of parallelism, however, it suffers from inefficiencies due to the dependencies between consecutive rows in a frame. We present three WPP implementations for HEVC CABAC decoding with improved parallel efficiency. The WPP versions based on more fine-grained dependency checks allow speed-ups up to 1.83x at very low implementation cost. We also present a bitstream partitioning scheme for future video compression standards. It enables additional parallelism in CABAC decoding by distributing syntax elements among eight bitstream partitions. Besides the parallelization opportunities, this allows specialization of the subdecoders responsible for the processing of their corresponding partitions as they have to process fewer types of syntax elements. This leads to further improvements in clock frequency and significant hardware savings compared to a full replication of the CABAC decoder as it is required for approaches such as WPP. Decoding speedups up to 8.5x at the cost of only 61.9% extra hardware area and less than 0.7% bitstream overhead for typical Full High Definition videos make this technique a promising candidate for use in future video compression standards. Furthermore, a cache-based architectural optimization is presented. It replaces the context model memory - a critical component in the CABAC decoder pipeline - by a smaller cache, thus increasing the achievable clock frequency. An application-specific adaptive prefetching algorithm is used together with a context model memory layout optimized for spatial and temporal locality. We perform a design space exploration of different cache configurations, finding that a cache of 2x8 context models provides the best performance. It allows for a 17% increase in clock frequency and miss rates of less than 2%, resulting in performance improvements up to 16.7%. We also propose techniques for more efficient CABAC decoding on general-purpose processors. Frequent hardly predictable branches lead to very inefficient implementations with these processors. Using more complex but linear arithmetic functions for the parallel decoding of binary symbols provides a speedup of up to 2.04x. A separate bitstream partition for this type of binary symbol even allows speedups up to 2.45x at the cost of not more than 0.2% higher bitrate for typical Full High Definition videos. Finally, we provide recommendations for future video compression standards and computer architectures as well as further research ideas for video coding in general and CABAC in particular. The research conducted in this thesis shows multiple approaches that can substantially improve the performance of CABAC decoding, thereby addressing one of the most critical throughput bottlenecks in modern video coding applications.
Cited by 0Open access
Fei Wei, Dajiang Zhou, Satoshi Goto · 2011
In this paper, we propose a full hardware encoder architecture for context-based adaptive binary arithmetic coding (CABAC) for Super Hi-vision data that tries to enlarge the throughput of the encoder. CABAC is a crucial part in H.264/AVC main profile that provides a great compression ratio at the expense of high computational complexity. Due to the data dependence between bit-wise processing, the throughput of the encoder is limited. Some techniques have been proposed in the latest encoder architecture designs to improve the speed to meet the need of QFHD or 3DHD applications. While for Super Hi-vision (4320p) case, a throughput of more than 1Gbps is required. While the current designs can only reach a throughput of around 660Mbps. As a result, frame parallelism is a usual but hardware costing way to solve the throughput gap. What's more, frame parallel will also cost frame delay problem, which is crucial in real-time system. This design tries to avoid the frame parallelism and save the power by encoding 4 bins per cycle using only one core, while working at a frequency of 264MHz. The technology used for synthesis is SMIC 90nm. Two main ideas are applied in this design to realize this high throughput.
Cited by 2
Xiaoliang Tian, Thinh M. Le, Hoong Chen Teo et al. · 2007
Cited by 0
Vivienne Sze, Anantha P. Chandrakasan · Journal of Signal Processing Systems · 2012
Cited by 5
2010
VHDL design implemented on a Xilinx FPGA. For each slice to encode, the CABAC core generates a compressed bitstream as specified by the ITU-T Video Coding Experts Group (VCEG) together with the International Standard Organization (ISO)/International Electrotechnical Commission (IEC)
Cited by 0
Alexander Alshin, Elena Alshina, JeongHoon Park · 2013
Entropy coding is the main important part of all advanced video compression schemes. Context-adaptive binary arithmetic coding (CABAC) is entropy coding used in H.264/MPEG-4 AVC and H.265/HEVC standards. Probability estimation is the key factor of CABAC performance efficiency. In this paper high accuracy probability estimation for CABAC is presented. This technique is based on multiple estimations using different models. Proposed method was efficiently realized in integer arithmetic. High precision probability estimation for CABAC provides up-to 1,4% BD-rate gain.
Cited by 23
Yongseok Choi, Jong-Bum Choi · Electronics Letters · 2013
A VLSI architecture of a context adaptive binary arithmetic coding (CABAC) entropy codec for high‐efficiency video coding (HEVC), the next generation video coding standard, is presented and analysis of its performance in terms of effective processing throughput, i.e. bin/s, is provided. For high throughput, the architecture is designed to process up to two regular bins per unit time while minimising pipeline stall due to inherent dependencies of CABAC through various optimisations including context forwarding and speculative decoding. The experiments show that the effective throughput is achieved up to 1.60 bins or 1.41 bits per cycle, which corresponds to 469.5 Mbit/s at the operating frequency of 333 MHz, under practical video coding environments.
Cited by 19Open access
Xiaohua Tian, Thinh M. Le, Yong Lian · Signals and communication technology · 2010
Cited by 1
Τυχάλας, Δημήτριος Κ. · University of Thessaly Institutional Repository (University of Thessaly) · 2017
Cited by 0Open access
YÜCEL ÇETİN · Kocaeli Üniversitesi - AVESİS · 2018
Cited by 0
Doohwan Kim, Jeonhak Moon, Seongsoo Lee · Journal of IKEEE · 2015
CABAC은 문맥 기반 적응적 이진 산술 부호화 방식으로, 이전까지 부호화 된 심볼들의 정보를 이용하여 확률을 업데이트하여 부호화 효율을 높이는 기법이다. 문맥 모델러는 통계적 상관성을 고려하여 심볼에 따라 확률 모델을 설계하는 CABAC의 핵심 블록으로서, 본 논문에서는 문맥 모델러의 효율적인 하드웨어 아키텍쳐를 제안한다. Verilog HDL로 기술되어 0.18 um 공정으로 설계된 문맥 모델러는 메모리를 포함하여 29,832개의 게이트로 이루어져 있으며, 최대 동작속도는 200 MHz, 최대 처리율은 200 Mbin/s이다. CABAC is a context-based adaptive binary arithmetic coding method. It increases the encoding efficiency by updating the probability based on the information of the previously coded symbols. Context modeler is a core block of CABAC, which designs a probability model according to the symbol considering statistical correlations. In this paper, an efficient hardware architecture of CABAC context modeler is proposed. The proposed context modeler was designed in Verilog HDL and it was implemented in 0.18 um technology. Its gate count is 29,832 gates including memory. Its operating speed and throughput are 200 MHz and 200 Mbin/s, respectively.
Cited by 3
Nana Shan, Wei Zhou, Zhemin Duan · Lecture notes in computer science · 2014
Cited by 0
Абаев, Е. М. · Репозиторий БГУИР (BSUIR Repository) · 2016
В докладе рассматриваются некоторые этапы реализации кодера CABAC стандарта H.264 на базе FPGA, а \nименно будет рассмотрен общий алгоритм работы кодера, а также схема электрическая структурная.
Cited by 0Open access