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About 2,106 papers for “CMOS ASIC”

Strahlungstolerantes Fluxgate CMOS Mixed Signal ASIC

Hauer, J., Oberst, M., Magnes, W. et al. · Publikationsdatenbank der Fraunhofer-Gesellschaft (Fraunhofer-Gesellschaft) · 2011

Für den Einsatz in Satelliten- und Weltraummissionen wurde eine CMOS Mixed Signalschaltung für die Auswertung von Fluxgate-Magnetometern, basierend auf einem DS-Konzept entwickelt. Das Verfahren zeigt einige wesentliche Neuerungen auf. So wird der externe Sensor ohne komplexe analoge Signalverarbeitung nur über einen Vorverstärker direkt an den DS-Modulator angekoppelt und über diesen ausgeregelt. Der Baustein wurde auf einer 0.35 um Standard CMOS Technologie implementiert. Die erforderliche Strahlungsfestigkeit konnte durch die Architekturwahl und die analoge Layoutoptimierung verbessert werden. Das Messsystem erreicht bei einer Bandbreite von 30 Hz einen Signalrauschabstand von 89 dB. Magnetische Feldstärken von < 10 Picotesla können damit erfasst werden. Der IC, der aus drei Magnetmesskanälen und einem Spannungsmesskanal besteht, benötigt 60 mW. Bei einer Strahlungsbelastung bis 170 krad Total Ion Dose (TID) blieb der Baustein innerhalb der spezifizierten Performance. Bei Belastungen bis 300 krad zeigte sich zwar eine Reduzierung des Signalrauschabstands und eine Erhöhung der digitalen Stromaufnahme, jedoch kein Funktionsausfall. Die Schwelle für Latchup-Effekte, Single Event Latchup (SEL) lag im digitalen Teil bei einer Cyclotron- Linear Energy Transfer (LET) von 14.1 MeV cm2 mg-1.

Cited by 0

CMOS ASIC (application specific integrated circuit)

L. Nuckolls · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 1989

This paper discusses the following topics: semicustom integrated circuits; radiation effects and hardness; circuit design considerations; the design cycle; fault analysis and design for test; and circuit layout.

Cited by 0Open access

Reliability Assessment of Cmos Asic Designs

M. S. Davies, P. D. T. O’Connor · 1990

A methodology is presented which aims to improve CMOS ASIC reliability. It differs from conventional reliability assessment techniques as it is based on an understanding of CMOS failure effects at the circuit-level. The first step of this approach requires a yield and failure analysis programme of CMOS ASICs to be established. The programme results are then used to simulate the effects of CMOS failures at the circuit-level and evaluate test patterns. The final step uses this knowledge to provide guidelines for test pattern generation and fault coverage comparisons.

Cited by 0Open access

A CMOS ASIC design for SiPM arrays

Samrat Dey, Lushon Banks, Shaw-Pin Chen et al. · 2011

Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM).

Cited by 11

New delay model for 0.5μ CMOS ASIC

Vassilios Gerousis, N. Pan, David Weaver · 2002

As silicon geometry moves closer to deep sub-micron (smaller than 0.5-/spl mu/m) technology, new physical phenomena start to appear and dominate the delay through an ASIC cell. As delays become smaller and the overall performance of applications increase, the emphasis on delay calculation accuracy increases. The authors demonstrate 0.5-/spl mu/m CMOS delay related physical phenomena such as coupling and shielding effects. They show how these components affect the cell and interconnect delays. The effects of these physical phenomena on CAD technology are discussed. A delay model for 0.5-/spl mu/m CMOS ASIC technology is described. This model takes into consideration the following items: unique 0.5-micron physical phenomena; optimization of ASIC library cell characterization time; speed of delay calculator CAD tool; the requirement of interconnect extraction and calculation accuracy; and the extensibility and flexibility of the model to provide additional accuracy for future silicon technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 0

The wavelet transform-a CMOS VLSI ASIC implementation

J.D. Hoyt, H. Weschsler · 2003

Describes a complementary metal oxide semiconductor (CMOS) very large scale integration (VLSI) application specific integrated circuit (ASIC) implementation of the wavelet transform. This custom hardware can provide higher speed, in the order of 5-50 million data samples/sec (needed for video applications) and/or lower power (needed for battery powered applications) than software implementations of either the wavelet or windowed Fourier transform on a conventional Von Neumann programmable computer.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 10

CMOS-ASIC life-predictions from test-coupon data

M. Buehler, N. Zamani, J. A. Zoutendyk · 2003

Establishes the design and test requirements for test structures fabricated in test coupons and demonstrates the use of test structure data in predicting the lifetime of long-life application-specific integrated circuits (ASICs). Data acquired from three CMOS reliability hazards, i.e., metal electromigration, hot carriers, and oxide breakdown, were used to calculate the cumulative-failure time dependence of CMOS ASICs. The experimental design required that test structures be replicated enough times on a wafer so that the structures can be stressed at three stress points, thus providing failure model parameters and their statistical distributions.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 1

CMOS Design of Pulse Processing ASIC for Radiation Detection

Vatsala Sharma, Kamal Nayanam · 2018

This paper presents the design & development of an 36 channel Pulse Processing ASIC using 0.35µm mixed CMOS technology for radiation detection in high energy physics experiments. The benefits of CMOS technology in nuclear instrumentation has surpassed the expectation due to advancement of technology, emerging detectors, readouts data rates and very important radiation hardness with benefits of low power and high density of electronics. The Pulse Processing ASIC intended to use with silicon pad detectors find application in high energy physics experiments for detecting nuclear radiations and converting the charge into electrical signals. The methodology of design includes circuit design and its optimization using public domain CAD tool.

Cited by 0

Implementation of a CMOS/MEMS Accelerometer with ASIC Processes

Yu-Sian Liu, Kuei-Ann Wen · Micromachines · 2019

This paper presents the design, simulation and mechanical characterization of a newly proposed complementary metal-oxide semiconductor (CMOS)/micro-electromechanical system (MEMS) accelerometer. The monolithic CMOS/MEMS accelerometer was fabricated using the 0.18 μm application-specific integrated circuit (ASIC)-compatible CMOS/MEMS process. An approximate analytical model for the spring design is presented. The experiments showed that the resonant frequency of the proposed tri-axis accelerometer was around 5.35 kHz for out-plane vibration. The tri-axis accelerometer had an area of 1096 μm × 1256 μm.

Cited by 14Open access

An ASIC Power Analysis System for Digital CMOS Design

Du Van Nguyen · PDXScholar (Portland State University) · 2000

Consumers demand for products with ever-increasing functionality, performance, and longer battery life is making low power a critical factor in most system designs. Lower-power designs are less expensive to produce, more reliable, and cost less to operate - factors which create a real competitive advantage. As a result, ASIC designers are demanding better ways to analyze the power of their designs. In this thesis, an ASIC Power Analysis System (APAS) is developed. APAS is an interactive simulation-based power analysis tool. Using a non-intrusive design technique, APAS can dynamically "snap on" to an existing simulation environment. APAS currently supports three ASIC simulators: QuickSim II, QuickHDL, and Verilog-XL, all with a common library. Diagnostics is one of the key features in designing APAS. APAS's hierarchical capabilities can be used to find out which blocks in the design are consuming the most power. The designer can then focus on reducing power in these blocks. Analyzing the dynamic behavior of the circuit is also key to power reduction. APAS can dynamically trace the power consumption of any block in the design, giving the user a graphical representation of the periods of high and low activity. The key to accuracy in APAS is the power models. APAS's power models represent dynamic switching, dynamic short-circuit and static currents. To Achieve optimum accuracy, APAS's models account for input slew, load and internal state. APAS's power models are written in the Power Modeling Format (PMF). PMF's combination of equations and interpolated tables provide the means to capture the most detailed cell characterization data under varying slew, load and state conditions. PMF is designed to support not only gates but also I/O cells, RAMs, and higher-level macros.

Cited by 2Open access

11-ps resolution time interval counter in CMOS ASIC

K. Klepacki, R. Szplet · 2012

This paper describes a design and test results of time interval counter (TIC), which provides a high resolution of 10.7 ps within a wide measurement range of 1 ms. To achieve these parameters the counting method with a two-stage interpolation within a single clock period is involved. A sub-gate delay resolution is obtained with the aid of the differential delay line technique. To diminish the nonlinearities of conversion and finally to improve the precision of measurement a novel matrix of differential delay lines is proposed. The TIC is implemented as an Application Specific Integrated Circuit (ASIC) in 0.35 μm CMOS process.

Cited by 3

A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

DuMonthier, J., Aslam, S., Quilligan, G. · NASA STI Repository (National Aeronautics and Space Administration)

A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

Cited by 0Open access

Asic Design of RF Energy Harvester Using 0.13UM CMOS Technology

Jainish K Zaveri · 2018

Recent advances in wireless sensor nodes, data acquisition devices, wearable and implantable medical devices have paved way for low power (sub 50uW) devices. These devices generally use small solid state or thin film batteries for power supply which need replacement or need to be removed for charging. RF energy harvesting technology can be used to charge these batteries without the need to remove the battery from the device, thus providing a sustainable power supply. In other cases, a battery can become unnecessary altogether. This enables us to deploy wireless network nodes in places where regular physical access to the nodes is difficult or cumbersome. This thesis proposes a design of an RF energy harvesting device able to charge commercially available thin film or solid-state batteries. The energy harvesting amplifier circuit is designed in Global Foundry 0.13um CMOS technology using Cadence integrated circuit design tools. This Application Specific Integrated Circuit (ASIC) is intended to have as small a footprint as possible so that it can be easily integrated with the above-mentioned devices. While a dedicated RF power source is a direct solution to provide sustainable power to the harvesting circuit, harvesting ambient RF power from TV and UHF cellular frequencies increases the possibilities of where the harvesting device can be placed. The biggest challenge for RF energy harvesting technology is the availability of adequate amount of RF power. This thesis also presents a survey of available RF power at various ultra-high frequencies in San Luis Obispo, CA.The idea is to determine the frequency band which can provide maximum RF power for harvesting and design a harvester for that frequency band.

Cited by 0Open access