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About 2,408 papers for “Dynamic random-access memory”

Dynamic computing random access memory

F L Traversa, F Bonani, Y V Pershin et al. · Nanotechnology · 2014

The present von Neumann computing paradigm involves a significant amount of information transfer between a central processing unit and memory, with concomitant limitations in the actual execution speed. However, it has been recently argued that a different form of computation, dubbed memcomputing (Di Ventra and Pershin 2013 Nat. Phys. 9 200-2) and inspired by the operation of our brain, can resolve the intrinsic limitations of present day architectures by allowing for computing and storing of information on the same physical platform. Here we show a simple and practical realization of memcomputing that utilizes easy-to-build memcapacitive systems. We name this architecture dynamic computing random access memory (DCRAM). We show that DCRAM provides massively-parallel and polymorphic digital logic, namely it allows for different logic operations with the same architecture, by varying only the control signals. In addition, by taking into account realistic parameters, its energy expenditures can be as low as a few fJ per operation. DCRAM is fully compatible with CMOS technology, can be realized with current fabrication facilities, and therefore can really serve as an alternative to the present computing technology.

Cited by 57Open access

Dynamic Random Access Memory industry

Lo, Matthew A. (Matthew Adam(/)) · DSpace@MIT (Massachusetts Institute of Technology) · 2012

Thesis (S.M.)--Massachusetts Institute of Technology, Sloan School of Management, 2012.

Cited by 0Open access

Embedded dynamic random access memory

T. Kirihata · 2004

For several decades, the 1-transistor Dynamic Random Access Memory (DRAM) has been the dominant choice for high density and low cost semiconductor memory in computing systems. Recently, advancements in miniaturization have allowed integration of DRAM on the same die with the processor. Key advancements in memory technology, architecture and circuit design required to capitalize on the merger of DRAM and logic are described here. After reviewing the history and accomplishments in embedded DRAM over the past decade, details of three generations of embedded DRAM development at IBM are discussed. In the third generation, which is the 130nm technology, three specialized DRAM macros have been developed. The first is a general purpose growable design targeted specifically for the ASIC's environment. The second is an area optimized design which includes special features for reducing standby and data retention current. The third macro employs a novel destructive read architecture with a single-ended direct sensing scheme for enabling random cycle time as fast as 3.3ns for network applications.

Cited by 3

A 256K dynamic random access memory

C.A. Benevit, J.M. Cassard, K.J. Dimmler et al. · IEEE Journal of Solid-State Circuits · 1982

A 5 V 256K/spl times/1 bit NMOS dynamic RAM employing redundancy is described. Using 2.3 /spl mu/m design rules, the cell is laid out in a folded bit line configuration having a row pitch of 6.5 /spl mu/m and a sense-amplifier pitch of 18 /spl mu/m. Tantalum silicide/polysilicon is used as the second polysilicon level to reduce the row line time constant. A storage capacitance of 60 fF and the Hi-C cell structure provides this memory with high alpha-particle insensitivity. The die measures 4.66/spl times/11.65 mm, and fits into a standard 0.3 in wide 16-pin DIP. The memory operates with 256 refresh cycles with a 4 ms refresh time. Typical RE/CE access times are 105/45 ns with an active power dissipation of 250 MW. Typical standby power is less than 20 mW. The part is compatible with the present Western Electric 5 V 64K part.

Cited by 36

Optical Dynamic Random Access Memory (ODRAM)

Gianluca Berrettini, L. Potì, Antonella Bogoni · 2011

An n-bit all-optical dynamic random access memory for write, read and refresh operation in optical computing applications is investigated. The 1-bit memory element obtained by a SOA-based variable optical buffer is verified and characterized.

Cited by 3

Improved performance of dynamic random access memory

Manjulata Sahoo · 2014

Dynamic Random Access Memory (DRAM) will lose its contents due to the leakage current of the capacitor present in it. Charge Retention capacity of DRAM is affected by leakage current.The temperature dependent current-voltage (I-V) characteristics of Ba(0.8)Sr(0.2)TiO(3) (BST) thin-film capacitors with and without ZrO(2) layer were studied in the temperature range of 400 to 450 K. It is observed that the leakage current is reduced for capacitors with ZrO(2) layer compared to those without this layer. The leakage current is dominated by Ohmic conduction mechanism in the low field region whereas space charge limited current (SCLC) mechanism contributes to the leakage current in the medium field region for both films. The activation energy (E(a)) for Ohmic conduction process is 0.5 eV for BST films and 0.56 eV for BST/Zr(O)2 multilayered film. The leakage current density is reduced by an order of magnitude for BST/ZrO(2) multilayered films compared to that of BST films in the whole electric field range. The estimated trap density (N(t)) decreases from 5.1 x 10^(18) to 2.2 x 10^(18) cm^(-3) with the insertion of Zr(O)2 layer. The observed reduced leakage current for capacitor with BST/ZrO(2) multilayer dielectric is due to the increase in the activation energy and decrease in the trap density and hence suitable for increasing the retention capacity of DRAM. Simulated leakage current density (J) versus electric field (E) is calculated for BST thin film capacitor at different temperatures and is compared with the experimental data. It is observed that the measured leakage current density is higher in comparison to simulated current density and is due to the effect of electrodes and dielectric thin film structure in a real capacitor.

Cited by 0

Three‐state dynamic random‐access memory (DRAM)

Supriya Karmakar · IET Circuits Devices & Systems · 2019

Abstract This work shows the design of three‐valued dynamic random‐access memory (DRAM) cell using quantum dot gate field effect transistor. DRAM is very popular for increasing device integration in integrated circuits. Storing multiple numbers of bits in a single DRAM cell increases the device integration further. The process technology is compatible with the conventional silicon process. The various write and read operations of the three‐value DRAM cell are also discussed in this work.

Cited by 0Open access

Synchronous Dynamic Random Access Memory (SDRAM) is

2008

The performance contributions of SDRAM address mapping techniques in the main memory of an embedded system are studied and examined. While spatial locality existing in the access stream increases SDRAM row hit rate, it also increases row conflicts. Mapping of the physical address bits into SDRAM column, row, bank and rank index impacts system performance significantly. A novel address mapping scheme, called bit-reversal, is described and experimentally compared against known methods. The bitreversal address mapping increases SDRAM row hit rate from 43 % to 66 % by distributing conflicting memory accesses over independent SDRAM banks. Bit-reversal address mapping reduces the average memory access latency by 26%-29 % over other methods, resulting in a 11.7%-13.5 % reduction of total execution time. The configuration space of bit-reversal address mapping is explored. Finally, limited studies examining the impact of address mapping techniques in conjunction with SDRAM controller policy and virtual paging illustrate that mapping is better suited to virtual memory free embedded systems than desktop workstations incorporating paging mechanisms.

Cited by 0

Differential vector storage for dynamic random access memory

Shokrollahi, Amin, Cronie, Harm · Infoscience (Ecole Polytechnique Fédérale de Lausanne) · 2016

A storage device stores data in groups of memory cells using vectors corresponding to voltage code codewords, each codeword having k entries. Entries have values selected from a set of at least three entry values and 2.sup.n distinct inputs can be encoded into k-entry codewords for some n>k. A vector storage element comprising k cells can store an k electrical quantities (voltage, current, etc.) corresponding to a codeword. The voltage code is such that, for at least one position of a vector, there are at least three vectors having distinct entry values at that position and, for at least a subset of the possible codewords, the sum of the entry values over the positions of the each vector is constant from vector to vector in that subset. The storage device might be an integrated circuit device, a discrete memory device, or a device having embedded memory.

Cited by 0Open access

A fault-tolerant 64K dynamic random-access memory

R.P. Cenker, D.G. Clemons, W.R. Huber et al. · IEEE Transactions on Electron Devices · 1979

A 64K dynamic MOS RAM with features and performance fully compatible with current 16K RAM's has been designed and characterized. The memory cell is a one-transistor-one-capacitor structure, standard except for a polysilicon bit line. A dual-32K architecture, along with partial selection and stepped recovery, holds power and peak current values below those of 16K parts. Spare rows and columns, which can be substituted for defective elements by the laser opening of polysilicon links, enhance yield. Worst case column enable access time of the memory is 100 ns, row enable access time is 170 ns, and only 128 cycles within 4 ms are needed to refresh the device.

Cited by 95

Embedded logic compatible dynamic random access memory design

He Yi · DR-NTU (Nanyang Technological University) · 2012

Logic-compatible 2T and 3T embedded DRAM (EDRAM) cells have recently gained their popularity in embedded applications because of their high density and good voltage margin. The most important design requirements in EDRAM cells are the cell area, data retention time and read speed. In the first part of this FYP, an in-depth analysis on the leakage mechanism and hence the retention time of the cells are carried out, followed by the impacts of several design factors (W, L, biasing voltage, and temperature). Finally, a systematic methodology is proposed for enhancing the retention time of the cell. Two representative EDRAM cells have been used to demonstrate the methodology. Simulation result using a standard 65 nm process shows that the data retention time is improved by more than 2.5X after optimization. In the second part of the report, the system level analysis is carried by using 128cells/column array and 256cells/column array, few techniques are proposed to further enhance the cell retention time and the cell performance, the comparison to the existing EDRAM cell design are also carried out.

Cited by 0

An 18K Bipolar Dynamic Random Access Memory Chip

R. F. Penoyer, B. El Kareh, R. Houghton et al. · 1980

A 2K × 9 bipolar dynamic random access memory (RAM) experimental chip is described with a 75ns and 300ns access and cycle time, respectively. The design is based on a two device cell of 800μm size and all chip input and output signals are TTL compatible.

Cited by 2

Logic-compatible embedded dynamic random access memory design

Yue Wang · DR-NTU (Nanyang Technological University) · 2014

Nowadays, EDRAMs become a new direction in the research society since it has higher density. However, poor data retention time due to small storage capacitor and various leakage paths has become the main issue, which results in high power consumption and poor read performance. In this FYP, the author develops two circuit techniques to improve the data retention time by analyzing the leakage currents of different EDRAM cell configurations. 
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\nFirstly, the author mainly discusses the effects of different design parameters on the data retention time. Basically, four parameters are talked about, which include gate biasing voltage of write transistor; body biasing voltage of write transistor; channel length of write/storage transistor and channel width of write/storage transistor. To optimize data retention time, a proposed procedure can be used. As a result, data retention time for Conv_P cell can be enhanced by more than 2.5 times by using 65nm process. 
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\nSecondly, in EDRAM cell design, PMOS transistor is more often used as write transistor since it has lower gate leakage compared with that of NMOS. To further improve its data retention time, different Vth transistor combinations are mainly concerned. Three configurations include Conv_P, Conv_N and C2T_PN cells are used to test. As a result, cells with HVth write transistor has much longer data retention time compared with LVth write transistor.

Cited by 0

Research progresses of dynamic random access memory devices

Peng‐Fei Wang, Yao Yao, Wu Jun et al. · Zhongguo kexue. Wulixue Lixue Tianwenxue · 2016

In this paper, the dynamic random access memory (DRAM) cell technology is introduced and the important technological breakthroughs are reviewed. The criteria of DRAM memory cell design is discussed and the key fabrication technologies of 6F<sup>2</sup> memory cell and stack capacitor DRAM cell are summarized. The technological evolution of array access transistor is also reviewed. The transistors with U-shaped transistor or FinFET and the fabrication process flow of 6F<sup>2</sup> DRAM chip were discussed. Based upon the technical requirements for DRAM cell, the possible device technologies for the next generation DRAM cell was summarized. It is predicted that (1) U-shape channel transistor will be the mainstream technology for the future DRAM cell beyond 20 nm; (2) low <italic>k</italic> material will be required for decreasing the bitline parasitic capacitance; (3) sense-amplifier with better signal-noise margin will be required to ease the requirement of high aspect-ratio storage capacitance; (4) low power DRAM design will draw more attention, rather than increasing the storage capacity of DRAM.

Cited by 0Open access

Memory row recording for mitigating crosstalk in dynamic random access memory

SeyedMohammad SeyedzadehDelcheh · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 2023

A method includes adding a set of one or more victim rows to a first probabilistic filter and to a second probabilistic filter, in response to a memory access request, identifying a candidate victim row adjacent to a memory address specified by a memory access request, identifying the candidate victim row as a victim row in the set of victim rows based on performing a lookup of the candidate victim row in a selected filter, where the selected filter includes one of the first probabilistic filter and the second probabilistic filter, in response to identifying the candidate row as the victim row, enabling a row hammering countermeasure, clearing the first probabilistic filter in each of a first set of time periods, and clearing the second probabilistic filter in each of a second set of time periods interleaved with the first set of time periods.

Cited by 0Open access