Raimund Ubar, Sergei Devadze, Jaan Raik et al. · 2008
A new improved method for calculation of fault coverage with parallel fault backtracing in combinational circuits is proposed. The method is based on structurally synthesized BDDs (SSBDD) which represent gate-level circuits at higher, macro level where macros represent subnetworks of gates. A topological analysis is carried out to generate an efficient optimized model for backtracing of faults to minimize the repeated calculations because of the reconvergent fanouts. The algorithm is equivalent to exact critical path tracing, however, processing the backtrace in parallel for a group of test patterns. Because of the parallelism, higher abstraction level modeling, and optimization of the topological model, the speed of fault simulation was considerably increased. Compared to the state-of-the-art commercial fault simulators the gain in speed was several times.
Cited by 11
N. Eva Wu · Automatica · 2004
Cited by 87
Microelectronics Reliability · 1990
Cited by 0
A.K. Majhi, Vishwani D. Agrawal · 2002
Failures that cause logic circuits to malfunction at the desired clock rate and thus violate timing specifications are currently receiving much attention. Such failures are modeled as delay faults. They facilitate delay testing. The use of delay fault models in VLSI test generation is very likely to gain industry acceptance in the near future. In this paper, we review delay fault models, discuss their classifications and examine fault coverage metrics that have been proposed in the recent literature. A comparison between delay fault models, namely, gate delay, transition, path delay, line delay and segment delay faults, shows their benefits and limitations. Various classifications of the path delay fault model, that have received the most attention in recent years, are reviewed. We believe an understanding of delay fault models is essential in today's VLSI design and test environment.
Cited by 37
Xiao Sun, C.C. Hull · 2002
It is shown that a functional verification coverage model based on functional property model is a super set of nonredundant physical stuck-at faults in this paper. This paper overviews a methodology to validate and verify hardware or software systems where the specification is modeled as a finite functional property model. The methodology proposed can produce a short verification/test with short verification and test application time and high design verification/physical fault coverage.
Cited by 2
S.R. Das, Asok Bhattacharyya · Electronics Letters · 1978
This letter develops an approach for fault detection and checking sequence design of sequential machines based on the principle of machine modification through augmentation of extra input and extra outputs, taking into consideration the case where faults occurring in a machine may cause an increase in its number of states.
Cited by 4
In Chip Interconnects, Yi Zhao, Student Member et al. · 2000
This paper addresses the problem of evaluating the effectiveness of test sets to detect crosstalk defects in system-level interconnects and buses of deep submicron (DSM) chips. The fast and accurate estimation technique will enable: 1) evaluation of different existing tests, like functional, scan, logic built-in self-test (BIST), and delay tests, for effective testing of crosstalk defects in core-to-core interconnects and 2) development of crosstalk tests if the existing tests are not sufficient, thereby minimizing the cost of interconnect testing.
Cited by 0
David Powell, Eliane Martins, Jean Arlat et al. · IEEE Transactions on Computers · 1995
This paper addresses the problem of estimating the coverage of a fault tolerance mechanism through statistical professing of observations collected in fault injection experiments. A formal definition of coverage is given in terms of the fault and system activity sets that characterize the input space. Two categories of sampling techniques are considered for coverage estimation: sampling in the whole space and sampling in a space partitioned into classes. The estimators for each technique are compared by means of hypothetical examples. Techniques for early estimations of coverage are then studied. These techniques allow unbiased estimations of coverage to be made before all classes of the sampling space have been tested. Then, the "no-reply" problem that hampers most practical fault-injection experiments is discussed and an a posteriori stratification technique is proposed that allows the scope of incomplete tests to be widened by accounting for available structural information about the target system.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 75
Jusas, V.,, Tamoševičius, Ž.,, Benisevičiūtė, R., · KTUePubl (Repository of Kaunas University of Technology) · 2004
The paper describes the most important elements for test performing in built-in-self-test circuit: linear feedback shift register and multiple-input signature register. The paper analyses the basic methods of using shift registers in built-in-self-test circuit. The paper presents a new combined method for built-in self test circuit. The combined method is a combination of pseudo random and deterministic test patterns generation. The main point of the new method – enabling to add deterministic test patterns into a sequence of pseudo random test. There are used decoder and correction logic. Test generation and signature analysis are done on BILBO register, which enables to perform both function on single device. Presented method enables to reach 100% of test efficiency and minimize the quantity of hardware.
Cited by 0Open access
J. Sosnowski · 2002
The paper is devoted to the problem of self-testing in system environment (field diagnosis and maintenance at the end user). It discusses test process decomposition in the context of increasing hardware complexity and proliferation of embedded DFT and BIST circuitry in the commercial off-the shelf VLSI chips (COTS). Test observability is improved with the use of various on-line monitoring mechanisms. To optimize test effectiveness we use special tools based on direct and indirect fault coverage analysis.
Cited by 0
R.S. Mejzak, K.T. Schmierer · 2002
The authors discuss the results of a Joint Integrated Avionics Working Group (JIAWG) evaluation of diagnostics initiative (JEDI) which is addressing the problem of accurately predicting and measuring fault detection, fault isolation, and other parameters of vendors' diagnostic designs. The JEDI program developed the metrics, methodology, and data package needed for the government to evaluate digital diagnostic designs at the module level. Lessons learned from the JEDI effort include: the use of fault simulation in verifying diagnostics is feasible; exhaustive fault simulation is not practical unless random sampling techniques are employed; and checkpoint restart capability is required of the simulator. The JEDI methodology and the data package are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 0
Jyotsna Sequeira, Suriyaprakash Natarajan, Prashant Goteti et al. · 2016
A practical fault simulation methodology for analog circuits in mixed-signal designs is presented. The methodology leverages the mixed-signal simulation environment of a product and performs mixed-signal fault simulation of embedded analog circuits. A set of open-circuit and short-circuit faults are extracted with guidance from layout parasitics, and automatically injected in to the net list. Fault coverage of manufacturing tests on faults in the transmitter of a high speed serial interface design are reported with two different observation criteria. Results indicate the amount of test reduction that can be achieved and the importance of appropriate observation in fault detection.
Cited by 8
2015
This chapter contains sections titled: Basic Types Imperfect Coverage Model Applications to Binary-State Systems Applications to Multi-State Systems Applications to Phased-Mission Systems Summary
Cited by 0
Wai Yie Leong · 1996
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Feng Li, Guoqing Wang, Meng Wang et al. · Journal of Computer Science and Technology · 2025
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W. Eric Wong, Yu Qi, Lei Zhao et al. · Proceedings - International Computer Software & Applications Conference · 2007
Localizing a bug in a program can be a complex and timeconsuming process. In this paper we propose a code coveragebased fault localization method to prioritize suspicious code in terms of its likelihood of containing program bugs. Code with a higher risk should be examined before that with a lower risk, as the former is more suspicious (i.e., more likely to contain program bugs) than the latter. We also answer a very important question: How can each additional test case that executes the program successfully help locate program bugs? We propose that with respect to a piece of code, the aid introduced by the first successful test that executes it in computing its likelihood of containing a bug is larger than or equal to that of the second successful test that executes it, which is larger than or equal to that of the third successful test that executes it, etc. A tool, ÷Debug, was implemented to automate the computation of the risk of the code and the subsequent prioritization of suspicious code for locating program bugs. A case study using the Siemens suite was also conducted. Data collected from our study support the proposal described above. They also indicate that our method (in particular Heuristics III (c), (d), and (e)) can effectively reduce the search domain for locating program bugs.
Cited by 205
D. Sidhu, T.-K. Leung · 2003
The authors present an estimation of fault coverage of four protocol test sequences generation techniques (T-, U-, D-, and W-methods) using Monte Carlo simulation on a simple protocol machine. The ability of a test sequence to decide whether a protocol implementation conforms to its specification heavily relies upon the range of faults that it can capture. This study shows that a test sequence produced by T-method has a poor fault detection capability whereas test sequences produced by U-, D- and W-methods have fault coverage comparable to each other and superior to that for T-method on several classes of randomly generated machines used.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 43
Basundhara Prasad · Lehigh Preserve · 1988
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Kevin A. Kwiat, Jr. Debany, Dussault Warren H. et al. · 1993
Abstract : Procedure 5012 governs the measurement and reporting of fault coverage for digital microcircuits. This report expands on the published version of Procedure 5012 and explains the rationale behind the requirements of the procedure. The complete text of 5012, with additional annotations, is included in this technical report.
Cited by 6
Jianwen Xiang, Fumio Machida, Kumiko Tadano et al. · IEEE Transactions on Reliability · 2014
This paper addresses the coverage (including identification and isolation) of irrelevant components in systems with imperfect fault coverage (IFC). In fault-tolerant systems, a single not-covered component fault may thwart the automatic recovery mechanisms, and lead to a system or subsystem failure. The models that consider the effects of IFC are known as coverage models (CMs). In traditional CMs, except those considering functional dependency (a similar concept to relevancy but with different assumptions and semantics), coverage is typically limited to faulty components regardless of their relevancies. Consequently, an operational but irrelevant component will not be isolated, and may threaten the system by its future uncovered (not-covered) failures. Although the system is generally assumed to be coherent, which implies the relevancy of each component in the initial system state, the traditional CMs do not consider the fact that an initially relevant component could become irrelevant after the failures of other components. We propose the irrelevancy coverage model (ICM) to cover the irrelevant components in addition to the faulty components. In the ICM, a component will be isolated from the system whenever it becomes irrelevant (even it is not failed), such that its future not-covered failures will not affect the system anymore. By incorporating the coverage of irrelevant components, the ICM opens up a new cost-effective approach to improve system reliability without additional redundancy.
Cited by 25