Axel Jantsch · 2023
The manipulation of Boolean functions is a central technique for the synthesis of hardware designs. Since digital designers need a basic understanding of the design techniques under the hood of synthesis tools, logic optimization and technology mapping are discussed in some detail in this chapter. The representation of data is critical for synthesis algorithms, because it determines the complexity of key operations. Binary decision trees are introduced as efficient internal data representation for logic functions because the key operations on Boolean functions can be implemented in polynomial time, which is not the case for sum of product or product of sum representations. As exemplary synthesis procedure, the two-level optimization algorithm proposed by Quine and McCluskey is studied in detail. Multi-level optimization and technology mapping are introduced and described only superficially.
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Sneh Saurabh · 2023
Chip designing is a complex task that requires an in-depth understanding of VLSI design flow, skills to employ sophisticated design tools, and keeping pace with the bleeding-edge semiconductor technologies. This lucid textbook is focused on fulfilling these requirements for students, as well as a refresher for professionals in the industry. It helps the user develop a holistic view of the design flow through a well-sequenced set of chapters on logic synthesis, verification, physical design, and testing. Illustrations and pictorial representations have been used liberally to simplify the explanation. Additionally, each chapter has a set of activities that can be performed using freely available tools and provide hands-on experience with the design tools. Review questions and problems are given at the end of each chapter to revise the concepts. Recent trends and references are listed at the end of each chapter for further reading.
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Hsiao-Yu Chiang, Yung‐Chih Chen, De-Xuan Ji et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2019
SAT Attack, CycSAT, and Removal Attack have demonstrated their abilities to break most existing logic locking methods. In this article, we propose a new cyclic logic locking method to invalidate these attacks simultaneously. Our main intention is to create noncombinational cycles to lock a circuit. Specifically, the noncombinational behavior in the noncombinational cycles that is unobservable at the primary outputs (POs) needs to be preserved when the correct key-vector is fed to resist CycSAT, and the noncombinational behavior in the noncombinational cycles affecting POs needs to be preserved when the incorrect key-vector is fed to invalidate SAT Attack. Furthermore, some nodes will be removed when applying our locking method, which is able to defend Removal Attack. The experimental results show the effectiveness and low area overhead of the proposed method.
Cited by 21
Jr. Sepe · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 2023
A method is provided for optimizing a rotating induction machine system fuzzy logic controller. The fuzzy logic controller has at least one input and at least one output. Each input accepts a machine system operating parameter. Each output produces at least one machine system control parameter. The fuzzy logic controller generates each output based on at least one input and on fuzzy logic decision parameters. Optimization begins by obtaining a set of data relating each control parameter to at least one operating parameter for each machine operating region. A model is constructed for each machine operating region based on the machine operating region data obtained. The fuzzy logic controller is simulated with at least one created model in a feedback loop from a fuzzy logic output to a fuzzy logic input. Fuzzy logic decision parameters are optimized based on the simulation.
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Martyn Edwards · Microprocessors and Microsystems · 1994
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J. M. Wilson · Journal of the Operational Research Society · 1998
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Pierre Genevès, Jean-Yves Vion-Dury · HAL (Le Centre pour la Communication Scientifique Directe) · 2004
XPath [5] was introduced by the W3C as a standard language for specifying node selection, matching conditions, and for computing values from an XML document. XPath is now used in many XML standards such as XSLT [4] and the forthcoming XQuery [10] database access language. Since efficient XML content querying is crucial for the performance of almost all XML processing architectures, a growing need for studying high performance XPath-based querying has emerged. Our approach aims at optimizing XPath performance through static analysis and syntactic transformation of XPath expressions.
Cited by 19Open access
Sudarsan Nanda · 2006
An Inventory Model of Deteriorating Items with Non-linear Fractional Objectives in Crisp Environment using Genetic Algorithm / Interactive Fuzzy Geometric Programming Method for Multi-objective Economic Inventory Model / Single Period Inventory of Differential Items Selling at Two Shops with Different types of Demand / Optimum Inventory Model of an Item Under a Sales Promotion Scheme / Generalized Invex Functionals and Some Duality Results in Banach Spaces / Multistage Allocation Process in Inventory Control Programming / Graceful Lobsters Obtained from Graceful Diameter Four and Six Trees / Convergence and Adjoint of Interval- Valued Fuzzy Matrices / Efficient Algorithms to Solve Disjoint Cliques Problem on Interval Graphs / Some Operators Defined Over Interval-Valued Intuitionistic Fuzzy Sets / Some Operations on Interval-Valued Intuitionistic Fuzzy Matrices / Generalized Convexity in Mathematical Programming / New Spectral Theorem for Vector Spaces Over Finite Fields Zp / Generalized Intuitionistic Fuzzy Sets and Some New Operators / Fuzzy Discriminant Analysis for Linguistic Variables.
Cited by 2
Category Cad Languages · 2007
With the advent of deep sub-micron technologies, interconnect loads and delays are becoming dominant. Consequently, the currently used design flow of iteratively performing logic synthesis with statistical wire-load models, doing placement & routing, extracting parasitics, and using them back in the synthesis tool runs into serious timing convergence problems. Layout-driven synthesis has become the need of the day. A number of researchers have addressed the problem of timing convergence and proposed a variety of solutions ranging from performing logic synthesis with estimates of physical information to combining specific sets of synthesis and physical design steps to postponing synthesis operations to a stage where more accurate physical information is available. However, there is currently no consensus among the design community as to the true solution of the timing convergence problem. Moreover, as designs get larger, designs constraints tighter and cost functions more varied and complicated, the problem is likely to assume even greater importance.
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Xin Xie (311744), Feng Huang (62988), Yefeng Long (20862460) et al. · Figshare · 2025
<div> SOC prediction is of great value to electric vehicle status assessment. Informer model is better than other models in SOC prediction, but there is still a gap in practical application. Therefore, based on the health assessment algorithm, a new optimized Informer model is proposed to predict SOC. Firstly, the health assessment is carried out through the historical running data of the electric vehicle to obtain the health matrix. Then, the health matrix is used to improve Encoder and Decoder modules and improve the prediction accuracy and speed of Informer model. Subsequently, the health matrix is utilized to optimize the prediction logic, reduce the influence of truncation error, and further improve the SOC prediction accuracy. Finally, using the Informer model before and after optimization, SOC prediction is performed using four different datasets. The results indicate that after optimizing the En-De module of Informer, prediction accuracy improved by approximately 15%, with prediction speed increasing by about 100%. Furthermore, optimizing the prediction logic to reduce truncation error further enhanced Informer’s prediction accuracy by around 20%. </div>
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Carragher Murgai Chakraborty, R. Carragher, R. Murgai et al. · 1999
With the advent of deep sub-microntechnologies, interconnect loads and delays are becoming dominant. Consequently, the currently used design flow of iteratively performing logic synthesis with statistical wire-load models, doing placement &amp; routing, extracting parasitics, and using them back in the synthesis tool runs into serious timing convergence problems. Layout-driven synthesis has become the need of the day. In this paper, we present a layout-driven optimization methodology that incorporates logic-level transformations for improving the delay and area of a mapped, block-placed, and globally routed design under certain constraints such as area availability, congestion, hold-time, and pin drive, etc. We argue that this is the right stage for optimization. Only those transformations that are local, incremental, and layout-friendly are incorporated. Examples of such transformations are net buffering, gate resizing, generalized DeMorgan transform, and pin permutation. We propose a sim...
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Sasao, Tsutomu · 1993
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Computers & Mathematics with Applications · 1996
Cited by 13
Yung‐Chih Chen, Li-Cheng Zheng, Hao-Ju Chang · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2023
In this article, we present a don’t-care-based threshold logic gate (TLG) minimization method for threshold logic network (TLN) optimization. We first introduce a sufficient condition for the don’t cares of a TLG to exist in a TLN and propose a logic-implication-based method to identify the don’t cares. Then, we present two different methods for minimizing the TLG with the don’t cares. The first one is an integer linear programming (ILP)-based method. We model the minimization problem as an ILP problem and propose an approach to compute the necessary constraints of the ILP formulation. The second one is a heuristic method adapted from a threshold function identification approach. In the experiments, we applied the proposed methods to two sets of TLNs generated by the up-to-date synthesis technique. The results show that, for the two sets of TLNs, the ILP-based method achieves an average of 12% and 23% area reduction without any overhead on the TLG count and logic depth. Furthermore, the heuristic method is more efficient than the ILP-based method with only a little quality loss.
Cited by 2
Sharad Malik · 1991
Designing an integrated circuit with over one hundred thousand components is a significantly complicated task; impossible to handle without computing aids. Computer-aided design tools are used in all aspects of the design: logical design of functional units, physical design of gates and modules, placement and interconnect routing, logical and timing verification, and management of design data. Of these, the automatic design of the logic components, referred to as logic synthesis, was the last to come about; an indication of the inherent difficulty of this task. There was a lack of sophisticated logic optimization techniques needed to generate high quality results. This prompted research in this area and as a result there are now several commercially available design aids. Thus far, logic synthesis has largely concentrated on combinational logic. This is an incomplete view, since digital circuits are, in general, sequential in nature. This thesis attempts to overcome this limitation. It presents techniques for the optimization of sequential logic circuits. In particular, it considers extensions of known combinational logic optimization techniques that are applicable in sequential logic synthesis. The contributions are in two areas. In the first part it is shown how existing combinational logic optimization techniques can be directly applied in the expanded context of sequential logic synthesis. The presented approach maximally exploits combinational logic optimization techniques, i.e. it can potentially detect any logical relationships that exist between any two gates in the circuit, they need not be part of the same combinational logic block. In the second part, techniques for the optimization of multi-level circuits with multiple-valued inputs are presented. Logic optimization techniques used in multi-level circuits have been extended to handle multiple-valued inputs. In addition to being a significant result in its own right, this has direct application in the state assignment problem in sequential logic synthesis. In both these areas, theoretical results are presented and implementation issues and practical experiences discussed.
Cited by 15
Rudolf H. Mak · Integration · 1984
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Tzi‐cker Chiueh · 2002
An architecture for implementing fuzzy-logic inference, together with the tools to optimally synthesize fuzzy logic circuits under this architecture, is proposed. The algorithms for finding the parameters for this architecture are presented. The author discusses how, computer-aided-design tools can be built to help fuzzy logic designers to explore the design space. In particular, the design process is divided into two phases, tuning the membership functions and synthesizing hardware implementations. The former is application-dependent, and previously no well-established automatic methods had been developed. A flexible, interactive design environment that allows designers to easily modify the plant model, the inference mechanism, and the membership functions, and quickly find out what the result is will be highly desirable.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Nathan Kitchen Andreas · 2005
Traditional approaches for sequential logic optimization include (1) explicit state-based techniques such as state minimization, (2) structural techniques such as retiming, and (3) methods that exploit sequential don&apos;t-cares derived from unreachable states. These approaches optimize a logic circuit as a single component with a single input/output behavior. In this paper we present a novel concept for sequential optimization referred to as temporal decomposition, which distinguishes the logic that initializes the circuit from the logic needed for the behavior after startup. This work was motivated by a recent observation made for bounded property verification: There is a substantial optimization potential for transition relations when the first execution steps are applied as satisfiability don&apos;t-cares. This result suggests that current designs include circuitry that is only used during the first few clock periods after reset and could be discarded or disabled after startup. In this paper we describe how temporal decomposition could be applied to treat the logic for startup separately from the remaining circuitry and discuss multiple alternatives to exploit this for an improved implementation.
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Yingping Wang (739697), Rui Yuan (615737), Xueying Tong (18778400) et al. · Figshare · 2024
<div><p>The escalating passenger flow in subway systems presents significant challenges to station facilities during peak hours. Poorly designed station facilities can reduce passenger throughput efficiency and compromise passenger safety. This study conducts on-site investigations to extract refined parameters of passenger behaviors in security check and ticket checking areas. Using Beijing Subway Yizhuang Line Ciqunan Station as a case study, a microscopic simulation model is developed to replicate pedestrian flow within the subway station. By focusing on passenger demand and traffic organization, the layout of station facilities is regulated and optimized. After optimization, the passenger density in the security check and ticket inspection areas during the morning peak period decreased from 1.33 people/m<sup>2</sup> to 1.00 people/m<sup>2</sup>; the longest queue length on the east side decreased from 15 people to 10 people, and the maximum queue length on the west side decreased from 7 people to 3 people. During peak hours, the dispersal time of passenger flow on the west side when entering the station decreased from 31.56 minutes to 30.04 minutes, and on the east side, it decreased from 36.12 minutes to 30.87 minutes. The optimization results effectively improved the efficiency of entering the station during peak hours.</p></div>
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Hooker, John N. · KiltHub Repository · 2018
This tutorial describes a logic-based approach to formulating and solving pure and mixed integer programming problems. It develops logical counterparts for ideas associated with traditional branch-and-cut methods, such as cutting planes, facet-defining cuts, relaxations, etc. The motivations for doing this are a) to exploit the structure of a wide range of problems that are too complex for polyhedral analysis, b) to take advantage of logic processing techniques developed for constraint programming and logic programming, and c) to provide a unified approach to solving the growing number of problems with both qualitative and quantitative elements
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