M. Ino, M. Togashi, S. Horiguchi et al. · 2003
An ultra-high-speed GaAs macrocell array is described which uses a three-level series-gate low-power source-coupled FET logic (LSCFL) as a basic circuit and a 0.4- mu m-gate flat-gate self-aligned implantation for n/sup +/-layer technology-2 (FG-SAINT-2) as a fabrication technology. The chip consists of 50 macrocells and is the equivalent of 250 gates. A typical propagation delay of unloaded ring oscillators and a typical toggle frequency of 1/4 frequency dividers fabricated on the macrocell array are 30 ps and 7.5 GHz, respectively. The basic cell is composed of three-level series gate LSCFL using all-differential signals; this circuit has twice the speed of a single-ended SCFL because it involves only one-half logic swing with the same noise margin. To verify the LSI performance, a 2*2 asynchronous transfer mode (ATM) switch element (150 equivalent gates) was fabricated on the macrocell array. The measured waveforms of the switch at 2 Gb/s are shown. The equivalent critical path gate number of the chip is 10 between flip-flops; therefore an average gate delay time of 50 ps is obtained.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 3
F.Distante Fdistante, M.G. Sami, R. Stefanelli et al. · 1990
Cited by 2
DISTANTE, FAUSTO, SAMI, MARIAGIOVANNA, STORTI GAJANI, GIANCARLO et al. · Virtual Community of Pathological Anatomy (University of Castilla La Mancha) · 1990
Cited by 2
CUHK Digital Repository (Chinese University of Hong Kong)
Cited by 0
Masao Suzuki, S. Konaka, H. Ichino et al. · IEEE Journal of Solid-State Circuits · 1985
A very high-speed 2500-gate Si bipolar macrocell array has been developed using a novel macrocell design approach and a 1-/spl mu/m rule advanced super self-aligned process technology (SST-1A). Using this macrocell array, a 16-bit parallel multiplier is designed and fabricated. The sophisticated circuit design of the macrocell array approach permits this complex function, which is equivalent to having 3024 NOR gates, using only 70% of the total of 756 internal cells. Consequently, a fast multiplication time of 7.5 ns is achieved with a 2.07-W power dissipation. Excellent performance with an average gate delay of 120 ps and average power dissipation of 0.365 mW is demonstrated for an equivalent NOR gate.
Cited by 8
Hallgren, Björn I, Rijssenbeek, M · CERN Bulletin · 1984
Cited by 0Open access
Jiuliasi Veiwili Uluiburotu, Koroi, Luke, Autiko D Loulou et al. · 2024
Cited by 0Open access
Jiuliasi Veiwili Uluiburotu, Luke Koroi, Autiko D. Loulou et al. · Lecture notes in networks and systems · 2026
Cited by 0
Sharif Mahmoud, Seedahmed, Hussain, Zahir, O'Shea, Peter · RMIT Research Repository (RMIT University Library) · 2004
Cited by 0
L.L. Li, S. Dong, Rong-Gui Du et al. · Dian hua xue/Dian huaxue · 2010
A single-dimensional array electrode was developed as a new electrochemical technique to image corrosion potential,galvanic current and polarization curves of reinforcing steel in concrete during corrosion process.Combining with the polarization behavior for each micro-electrode,the interactions between corrosion macrocell and corrosion microcell of the steel in concrete were evaluated.It was noticed that the corrosion macrocell and microcell occurred independently in difference regions at the initial stage of corrosion.The corrosion macrocell current can be in situ followed by corrosion potential imaging.The corrosion propagation of steel in concrete is closely related to the interactions between corrosion macrocell and corrosion microcell.
Cited by 0Open access
Erika Y. Lin, Steven J. E. Wilton · 2001
. We examine ways to increase product term usage e#ciency and propose several new sharing architectures that addresses this problem. We also present a technology mapping algorithm for product term based FPGA embedded memory arrays. Our algorithm, pMapster, is used to investigate the e#ects of macrocell granularity and macrocell sharing on the amount of logic that can be packed into a product term embedded memory array. 1
Cited by 0
G. White · Radio and Electronic Engineer · 1970
An iterative array of macro-cells is proposed to multiply together two N digit decimal numbers with a propagation delay of (2N − 1) macrocell delays. The array will also add two decimal numbers to the product without adding to the complexity.
Cited by 0
Seedahmed S. Mahmoud, Zahir M. Hussain · 2015
Abstract:- We present a single input – multiple output (SIMO) time-varying wireless vector channel model for a macrocell mobile environment. This model is based on the assumption that the distances between the mobile and the local scatterers and the local scatterers and the dominant scatterers are distributed according to the inverse cosh-squared function. The channel model allows investigation of beamforming aspects as well as space-time processing techniques. Keyword:- Antenna array; multipath components; macrocell; SIMO. 1
Cited by 0
Muye Yang, Shigenobu Kainuma · Figshare · 2021
To examine the macro-galvanic corrosion of carbon steel near the air–liquid interface, a test panel of array electrodes was developed for investigating the corrosion behaviour in NaCl solution and wet soil environment. The corrosion rates were evaluated by electrochemical approaches and verified by the corrosion exposure tests. The analysis focused on the interaction between the macrocell and microcell according to the ZRA, EIS, and OCP measurements. Test results reveal that the coexisting of macrocell and microcell corrosion would change the position of maximum corrosion, and it was inferred the relationship of actual current density and microcell current density. In addition, the wet soil environment shows both microcell and macrocell corrosion near the air–liquid interface should be more severe than that in an iso-concentrated NaCl aq environment, whereas its macro-galvanic interaction of steel at the deep region should be smaller due to the low-diffusion rate in the soil environment.
Cited by 0Open access
Yang, Muye, Kainuma, Shigenobu · Figshare · 2021
To examine the macro-galvanic corrosion of carbon steel near the air–liquid interface, a test panel of array electrodes was developed for investigating the corrosion behaviour in NaCl solution and wet soil environment. The corrosion rates were evaluated by electrochemical approaches and verified by the corrosion exposure tests. The analysis focused on the interaction between the macrocell and microcell according to the ZRA, EIS, and OCP measurements. Test results reveal that the coexisting of macrocell and microcell corrosion would change the position of maximum corrosion, and it was inferred the relationship of actual current density and microcell current density. In addition, the wet soil environment shows both microcell and macrocell corrosion near the air–liquid interface should be more severe than that in an iso-concentrated NaCl aq environment, whereas its macro-galvanic interaction of steel at the deep region should be smaller due to the low-diffusion rate in the soil environment.
Cited by 0Open access
Jason Cong, Hui Huang, Xin Yuan · ACM Transactions on Design Automation of Electronic Systems · 2005
In this article, we study the technology mapping problem for a novel field-programmable gate array (FPGA) architecture that is based on k -input single-output programmable logic array- (PLA-) like cells, or, k/m -macrocells. Each cell in this architecture can implement a single output function of up to k inputs and up to m product terms. We develop a very efficient technology mapping algorithm, k_m_flow, for this new type of architecture. The experimental results show that our algorithm can achieve depth-optimality on almost all the testcases in a set of 16 Microelectronics Center of North Carolina (MCNC) benchmarks. Furthermore it is shown that on this set of benchmarks, with only a relatively small number of product terms ( m ≤ k + 3), the k/m -macrocell-based FPGAs can achieve the same or similar mapping depth compared with the traditional k -input single-output lookup table- ( k -LUT-) based FPGAs. We also investigate the total area and delay of k/m -macrocell-based FPGAs and compare them with those of the commonly used 4-LUT-based FPGAs. The experimental results show that k/m -macrocell-based FPGAs can outperform 4-LUT-based FPGAs in terms of both delay and area after placement and routing by VPR on this set of benchmarks.
Cited by 27
X. Hu, Meiyuan Wang, M. Zhang · 2002
BiCMOS gate array circuits and macrocell libraries are designed and fabricated through 2.0 /spl mu/m BiCMOS standard processes. The average gate delay time is as follows: BiCMOS 21 stage inverter, 1.1 ns; BiCMOS 21 stage oscillator, 1.1 ns; BiCMOS 21 stage NAND, 1.3 ns; BiCMOS 21 stage NOR, 1.4 ns. BiCMOS 500 gate array circuits are optimized and 2000 gate array circuits are designed. The delay time of BiCMOS is less than CMOS with large load capacitance.
Cited by 0
Marios Kountouris, Nikolaos Pappas · arXiv (Cornell University) · 2013
We consider a heterogeneous cellular network (HetNet) where a macrocell tier with a large antenna array base station (BS) is overlaid with a dense tier of small cells (SCs). We investigate the potential benefits of incorporating a massive MIMO BS in a TDD-based HetNet and we provide analytical expressions for the coverage probability and the area spectral efficiency using stochastic geometry. The duplexing mode in which SCs should operate during uplink macrocell transmissions is optimized. Furthermore, we consider a reverse TDD scheme, in which the massive MIMO BS can estimate the SC interference covariance matrix. Our results suggest that significant throughput improvement can be achieved by exploiting interference nulling and implicit coordination across the tiers due to flexible and asymmetric TDD operation.
Cited by 39Open access
Takayuki Kaneko, Y. Akazawa, Mitsuyoshi Nagatani · 1991
An automatic macrocell generator has been developed and applied to the analog layout of switched-capacitor (SC) and active-RC filters. The generator consists of a process-independent generation procedure, a leafcell library, and a circuit description of the leafcells. The unit element arrays of the whole filter are generated together to minimize the array height of the entire filter macrocell, so that the area of the generated filter is as small as that of a manually laid out filter. Three SC filters and one active-RC filter were designed and fabricated by 1.5- mu m CMOS technology and successfully yielded a signal-to-noise (S/N) ratio of more than 70 dB with a quick turnaround time.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 3
N. Indira Devi, Rajarshi Mahapatra, Vinod Kumar Reddy et al. · 2016
Today's wireless environment is very dense to support enhanced performance, which is become heterogeneous in cell, applications, services, standards and technologies. This dense deployment of heterogeneous cells has a large impact on the power consumption of network. Thus, issue of energy efficiency need to be considered in perspective of deploy of several base station (BS) in the area. In 5G standard, massive MIMO architecture has been proposed to enhance energy efficiency (EE) of network. In this paper, we have considered the heterogeneous network (HetNet), where microcell, picocell and femtocell are coexist within macrocell. The macrocell BSs (MBS) are equipped with large array of antennas and all other BSs are supported with limited number of antennas. This work assumes users are supported by massive MIMO architecture, where MBS and few nearest BSs are participated. In this paper, we mainly investigate the impact of deployment efficiency of heterogeneous small cells BSs and, user association in a HetNet with massive MIMO to maximize the system energy efficiency (EE). Our results show that involvement of nearest BSs is greatly enhance the system energy efficiency (EE) and the deployment efficiency of small cells in macrocell environment also have impact on system EE.
Cited by 1