Amit Dogra, Taqdir · International Research Journal on Advanced Engineering Hub (IRJAEH) · 2024
It is critical to identify Distributed Denial of Service (DDoS) attacks to preserve network integrity and guarantee continuous service delivery. Our research suggests a novel way to lower the network's packet drop ratio and improve the accuracy of DDoS attack detection. Conventional techniques occasionally just use anomaly detection or signature-based detection, which might not be sufficient to protect against DDoS assault schemes that are always changing. To increase the precision and resilience of DDoS detection, our system incorporates several detection strategies, such as signature-based, anomaly-based, and machine learning-based techniques. Additionally, we use network traffic analysis and anomaly detection tools to quickly discover and block harmful traffic patterns. During suspected DDoS attempts, we dynamically modify network parameters and reroute data to reduce the packet drop ratio and maintain service for authorized users. Additionally, our system has feedback systems that allow us to continuously adjust and improve detection algorithms, improving the overall dependability and effectiveness of DDoS attack detection. We illustrate how successfully our method lowers packet drop ratios and strengthens network resilience against DDoS attacks using both simulation and real-world experience.
Cited by 4Open access
Y. Y. Du, Keyang Chang, Jinglin Shi et al. · 2023
As the Internet of Things becoming widely used, the requirement for high performance network is growing rapidly. Network performance is affected by data transmission based on physical link and packet processing handled by operating system. With the development of network hardware technology and wireless communication technology, network data transmission rate has been further improved, but the packet processing performance based on operating system cannot match it. There are several performance bottlenecks in the traditional packet processing, correspondingly there are various optimization mechanisms to solve these problems and further improve the performance. This paper analyzes some mainstream optimization mechanisms of packet processing based on software. Firstly, we analyze the architecture design of these mechanisms and the workflow when receiving packets. Then we compare the technical methods adopted by each mechanism and problems solved by each mechanism. Finally, we compare the application scenarios and the shortcomings of each mechanism.
Cited by 3Open access
Alireza Farshin, Tom Barbette, Amir Roozbeh et al. · 2021
We present PacketMill, a system for optimizing software packet processing, which (i) introduces a new model to efficiently manage packet metadata and (ii) employs code-optimization techniques to better utilize commodity hardware. PacketMill grinds the whole packet processing stack, from the high-level network function configuration file to the low-level userspace network (specifically DPDK) drivers, to mitigate inefficiencies and produce a customized binary for a given network function. Our evaluation results show that PacketMill increases throughput (up to 36.4 Gbps -- 70%) & reduces latency (up to 101 us -- 28%) and enables nontrivial packet processing (e.g., router) at ~100 Gbps, when new packets arrive >10× faster than main memory access times, while using only one processing core.
Cited by 44Open access
John J. Leddy, Daniel Voyer, S. Matsushima et al. · 2021
The SRv6 Network Programming framework enables a network operator or
an application to specify a packet processing program by encoding a
sequence of instructions in the IPv6 packet header. Each instruction
is implemented on one or several nodes in the network and identified
by an SRv6 Segment Identifier in the packet. This document defines the
SRv6 Network Programming concept and specifies the base set of SRv6
behaviors that enables the creation of interoperable overlays with
underlay optimization.
Cited by 105
R. Ramaswamy, Tilman Wolf · 2004
Network processing is becoming an increasingly important paradigm as the Internet moves towards an architecture with more complex functionality inside the network. Modern routers not only forward packets, but also process headers and payloads to implement a variety of functions related to security, performance, and customization. It is important to get a detailed understanding of the workloads associated with this processing in order to be able to develop efficient network processing engines. We present a tool called PacketBench, which provides a framework for implementing network processing applications and obtaining an extensive set of workload characteristics. PacketBench provides the support functions to handle various packet traces and manage packet memory. For statistics collection, PacketBench provides the ability to derive a number of microarchitectural and networking related metrics. We present the results of such measurements for four different networking applications ranging from simple packet forwarding to complex packet payload encryption. The results show that such workload analysis has a range of uses from network processor design to application optimization.
Cited by 99
Mitsuhiro Miyazaki · 2002
The explosive growth of the Internet and e-business requires faster deployment of high-bandwidth equipment, greater flexibility to support emerging Internet technologies, and new services within the network. The design of routers is being changed significantly by the emergence of Network Processors (NPs). With programmable NPs, exceptionally fast packet processing at high-bandwidth is achieved through the optimization of both the instruction set and data path. Routers have to perform complicated protocol stack processing with demands for various services. However, the fast packet switching path, namely the packet forwarding path with table look-up, filtering, queuing assignment and input/output scheduling, influences network performance more than the slow packet switching path. This paper characterizes router processing with pseudo code based on the fast path for an emerging network processor, the Intel IXP1200. It also addresses the workload characterization of the fast path in routers. I expect that those characterizations should be very useful to guide the architectural design of future
Cited by 0
2013
Cloud based network services typically have high-performance packet processing requirements. This reference architecture documents data and learnings from configuring and testing a virtualized packet processing environment using Linux * with a Next Generation Communications Platform from Intel, codename Crystal Forest. The primary audiences for this reference architecture (RA) are architects and engineers evaluating Intel ® architecture based solutions for cloud based network services where packet processing performance is a key requirement. The RA provides details for setting up, configuring, and testing a virtualized packet processing environment using Linux * on a Next Generation Communications Platform from Intel with the codename Crystal Forest. The system tested was a dual Intel ® Xeon® ATCA reference platform with Intel ® Xeon ® processor E5-2600 series and the Intel® 82599 10 Gigabit Ethernet Controllers (formerly Niantic). Performance information applies to the target platform; however the test methodology and optimization learnings are more generally applicable to packet handling solutions
Cited by 0
FAN Hongwei,HU Yuxiang,LAN Julong · SHILAP Revista de lepidopterología · 2018
In order to improve the packet processing performance of Virtual Network Function(VNF),this paper comes up with a Field Programmable Gate Array(FPGA)-based General Hardware Accelerator(GHA) architecture.The GHA architecture implements the packet processing pipeline on a dynamically reconfigurable FPGA,increasing VNF throughput and ensuring independence between different VNF accelerators.The Discrete Particle Swarm Optimization(DPSO) algorithm is utilized to optimize the allocation of acceleration resources.Experimental results indicate that GHA architecture can increase the throughput of VNF by 50.7 times approximately,and the optimization rate of the acceleration resource allocation strategy can reach 24.5%.
Cited by 0Open access
Kirill Kogan, Sergey Nikolenko, Vitalii Demianiuk et al. · 2018
In this work, we draw from our research and industry experience in the design of networked systems and define research directions that can simplify management and better exploit network infrastructure. We introduce problems both on data and control planes related to the design of a single network element and network-wide behaviors, concentrating on three directions: processing a single packet with packet classifiers, processing streams of packets in network switches, and network-wide control plane optimization. In particular, we consider efficient representations of packet classifiers, expressive implementations of buffer management policies, the composition of heterogeneous control planes, network virtualization, and extension of the network stack to support interactive applications. For the considered research directions outlined here, we formulate problems that, we believe, are important in the design of network systems. The purpose of this work is to attract system researchers to specific problems introduced in this paper.
Cited by 0
Christian Sieber, Raphael Durner, Maximilian Ehm et al. · 2017
Network Functions Virtualization (NFV) aims to move network functions away from expensive hardware appliances to off-the-shelf server hardware. NFV promises higher flexibility and cost reduction for the network operator. In order to achieve high throughput performance with this commodity hardware, fast packet processing frameworks like NetMap or the Data Plane Development Kit (DPDK) can be used. It is known that packet processing performance is very sensitive regarding copying of packets. In this paper we take steps towards quantifying the efficiency of NFV regarding packet copying overhead at hardware level. As modern servers are often built up of multiple CPUs with segregated memory, we evaluate the performance penalties resulting from this segregation in conjunction with DPDK. Additionally we evaluate the effects of cache misses on packet processing in detail. Subsequently a metric that quantifies the efficiency of a running VNF is introduced and an optimization scheme is outlined which describes the use of the metric. Our results show how both cache misses and memory segregation reduce the network efficiency.
Cited by 16
Ralph Duncan, Peder Jungck, Kenneth A. Ross · Apress eBooks · 2011
Network packet processing applications increasingly execute at speeds of 1–40 gigabits per second, often running on multi-core chips that contain multithreaded network processing units (NPUs) and a general-purpose processor core. Such applications are typically programmed in a language that exposes NPU specifics needed to optimize lowlevel thread control and resources. This facilitates optimization at the cost of increased software complexity and reduced portability. In contrast, our approach provides portability by combining coarse-grained parallelism with programming in the packetC® (CloudShield Technologies) language's high-level constructs. This paper focuses on searching packet contents for packet protocol headers. We require the host system to locate headers for layers 2, 3 and 4, and to encode their offsets in a packet information block (PIB). packetC provides descriptors, C-style structures superimposed on the packet array at runtime-calculable, user or PIB-supplied offsets. We deliver state-of-the-practice performance via an FPGA for locating layer offsets and via micro-coded interpretation that treats PIB layer offsets as a special addressing mode.Keywordsprogramming languagespacketCnetwork processingparallel processing
Cited by 0
Y. Wang, V. S. Pakki · 2014
The main objective of this Master Thesis is to design and implement a high level synthesis tool for high speed packet processing. For a given network packet, determining the destination and performing the required alterations to the packet are the key parts of Packet Processing. The idea is to provide customers a customized Ethernet switch which is reliable and flexible. As a requirement for this, a high level packet processing language (PPL) is designed instead of any hardware descriptive language because of the regularity of packet processing. The packet processing is described in a powerful way based on the PPL. In this thesis, a design of Ethernet switch based on the PPL is proposed. Hardware implementation is done for the design and MyHDL is used as the hardware description language. Using Python, the compiled PPL program is translated into an hardware model. A tool has been developed which consists of a hardware generator and certain hardware infrastructures. Another part in the thesis is optimization of the initial design. For instance, optimization is done to run as much code as possible in parallel or for removal of unused hardware in the generated switch. Verification is done and synthesis results have been listed comparing the two designs. Hence, we conclude that the initial design is more flexible and has more redundancy while the optimized design is more friendly to hardware cost and power consumption.
Cited by 0
Bin Ren · 2011
A fast method based on wavelet packet and GA-BP neural network was proposed according to the traditional method of estimating red jujube disease which were slow and arduous.Firstly,a wavelet packet image processing method was used to remove the interference caused by random noise produced during the image acquisition process,and then the singular value of the wavelet packet decomposition coefficient matrix and the wavelet packet transform modulus maxima matrix was used to construct the characteristic vector.Finally,the BP neural network that the genetic algorithm has improved was used to establish red jujube pest image recognition model.Experimental results show that the method wavelet packet and genetic algorithm combined with neural network can realize accurate and fast recognition for the red jujube disease image.The accuracy reaches more than 97 percent and the time of recognition model after the genetic algorithm optimization reduces to one ninth of the original.
Cited by 1
Michael K. Chen, Xiao Feng Li, Ruiqi Lian et al. · 2005
Programming network processors is challenging. To sustain high line rates, network processors have extremely tight memory access and instruction budgets. Achieving desired performance has traditionally required hand-coded assembly. Researchers have recently proposed high-level programming languages for packet processing, but the challenges of compiling these languages into code that is competitive with hand-tuned assembly remain unanswered. This paper describes the Shangri-La compiler, which accepts a packet program written in a C-like high-level language and applies scalar and specialized optimizations to generate a highly optimized binary. Hot code paths identified by profiling are mapped across processing elements to maximize processor utilization. Since our compilation target has no hardware caches, software-controlled caches are generated for frequently accessed application data structures. Packet handling optimizations significantly reduce perpacket memory access and instruction counts. Finally, a custom stack model maps stack frames to the fastest levels of the target processor’s heterogeneous memory hierarchy. Binaries generated by the compiler were evaluated on the Intel IXP2400 network processor with eight packet processing cores and eight threads per core. Our results show the importance of both traditional and specialized optimization techniques for achieving the maximum forwarding rates on three network applications, L3-
Cited by 0
Mohammad Anbar, Deo Prakash Vidyarthi · International Journal of Interdisciplinary Telecommunications and Networking · 2011
A Cellular IP (CIP) network involves a bulk of data transmission. It is highly reliable and guarantees the safe delivery of the packets required in such systems. Reliable traffic performance leads to efficient and reliable connectivity in Cellular IP network. CIP network, which consists of mobile hosts, base stations, and links, are often vulnerable and prone to failure. During the routing operation in the network, the base station, which works as router for the transmitted packets, may fail to perform. Reliable transmission is desirable, in terms of services of the base stations in the network, reliable routing, and processing the data. In this paper, the authors design a reliability model to increase the reliability of a flow, consisting of packets, passing through routers in a Cellular IP network. Particle Swarm Optimization (PSO) is able to solve a class of complex optimization problems. PSO is used to improve the reliability of the flow in CIP network. The proposed model studies the effects of packet processing rate (), packet arrival rate (), and the number of packets per flow on the reliability of the system. A simulation experiment is conducted and results reveal the effectiveness of the model.
Cited by 1
Alex Davydow, Pavel Chuprikov, Sergey Nikolenko et al. · 2017
Modern datacenters are increasingly required to deal with latency-sensitive applications. A major question here is how to represent latency in desired objectives. Incorporation of multiple traffic characteristics (e.g., packet values and required processing requirements) significantly increases the complexity of buffer management policies. In this work, we consider weighted throughput optimization (total transmitted value) in the setting where every incoming packet is branded with intrinsic value, required processing, and slack (an offset from the arrival time when a packet should be transmitted), and the buffer is unbounded but effectively bounded by slacks. The main result is a 3-competitive algorithm as the slack-to-work ratio increases. Our results supported by a comprehensive evaluation study on CAIDA network traces.
Cited by 7
Sam , Poh Mun · Universiti Sains Malaysia Institutional Repository (Universiti Sains Malaysia) · 2016
This research investigates the method to improve the data transmission throughput in a networking system. The reason of this research proposal is because of computer network has grown tremendously in recent years and it requires to handle more complex data packet with different sizes from applications. In this research, the throughput for various packet sizes used in a data transmission system were analyzed. The common network frameworks may not be efficient in handling the data traffic with random packet size especially when there are many small packet frames. Therefore, the optimization on the network framework is necessary to improve the packet processing throughput for small packet size. Investigation in methods to improve the local memory accessing rate in processor and network device were conducted. In addition, the duplication of memory address from system memory to cache is reduced by implementing Huge Page Table. Then, the impact on low throughput due to the context switching overhead originated from the system and device interrupts were analyzed. The interrupt polling mechanism were implemented on receive and transmit paths of the network driver for reducing the overheads. Another improvement introduced was by enabling the burst mode in the receive port. This will make the incoming packets being received and processed in bulk, and therefore removing the latency of processing each packet individually. The proposed improvements have been implemented on a Data Plane Development Kit (DPDK) framework and tested on the hardware using simulated data traffic. The results showed that the improved framework is able to achieve better network throughput by 61% compared to the conventional framework particularly for small packet size.
Cited by 0Open access
Ivan Ivanets, V. Ovsyak, O. Ovsyak · Vìsnik Nacìonalʹnogo unìversitetu Lʹvìvsʹka polìtehnìka Serìâ Ìnformacìjnì sistemi ta merežì · 2025
Hybrid Fiber-Coaxial networks remain a critical broadband infrastructure, enabling high-speed Internet access for millions of users worldwide. However, as demand for low-latency, high-bandwidth applications such as cloud computing, 4K/8K streaming, and online gaming continues to grow, traditional packet processing architectures struggle to meet performance requirements due to high CPU utilization, inefficient transport-layer processing, and limited scalability. Existing Hybrid Fiber-Coaxial network modernization strategies typically involve Distributed Access Architecture implementation, full network migration to fiber, or DOCSIS 4.0 upgrades. While these approaches enhance capacity and efficiency, they require significant capital investments, extensive infrastructure upgrades, and complex integration with existing operator networks. A cost-effective alternative is the optimization of packet processing efficiency using software-defined networking solutions, reducing network congestion and improving latency without requiring hardware overhauls. This paper proposes a software-driven performance enhancement for Hybrid Fiber-Coaxial networks using The Fast Data Project VPP HostStack, a high-performance, user-space networking stack that minimizes packet processing latency and optimizes throughput without requiring physical network modifications. By leveraging vectorized execution, zero-copy data movement, and optimized memory management, VPP HostStack achieves significant performance improvements, reducing latency, increasing TCP/UDP throughput, and lowering CPU utilization compared to traditional kernel-based network stacks. To validate the efficiency of VPP HostStack, a CSIT-based benchmarking methodology was employed to measure packet loss, latency, and throughput under different traffic scenarios. Thus, VPP HostStack presents a scalable and cost-effective solution for improving HFC network performance, allowing operators to enhance broadband infrastructure without the substantial financial and technical burden associated with fiber migration, Distributed Access Architecture rollouts, or full- scale DOCSIS 4.0 deployments. This research contributes to the evolution of Software-Defined Networking and high-performance traffic processing, providing a viable alternative for Internet Service Providers seeking to modernize HFC networks while minimizing capital expenditures.
Cited by 0Open access
S. Sankar Ganesh, S. Rajaprakash · International Journal of Communication Systems · 2021
Summary Underwater acoustic sensor network (UASN) employs to monitor the aquatic environment. The underwater nodes deploy for continuous and real‐time monitoring. The underwater nodes deploy at different depths to facilitate data forwarding from ocean floor sensor to buoys node. However, the underwater network has limited network resources such as the battery, bandwidth, and susceptibility to mobility, thermographic conditions, and propagation delay. The propagation delay and thermographic condition prolong node packet processing and delay network operation. The delayed network operation increases node battery consumption and overhead. Hence, a bio‐inspired dolphin swarm optimization algorithm (DSA) implements to select the optimal antenna for data transmission. The DSA selects the optimal antenna for data communication by evaluating the acknowledgment packet obtained for data transmitted through multiband antennas. The DSA was simulated in an NS2‐Aquasim environment and testbed to evaluate its performance. The DSA improved data reliability, packet delivery ratio by 97%, and reduced bit error rate (BER), end‐to‐end delay compared to traditional algorithms.
Cited by 3
Damian Mroziński, Mirosław Klinkowski, Krzysztof Walkowiak · 2023
We analyse the impact of Network Slicing (NS) on the performance of a packet-switched xHaul transport network carrying the radio data traffic in a 5G Radio Access Network (RAN). Two 5G services / slices of different requirements, namely, Enhanced Mobile Broadband (eMBB) and Ultra Reliable Low Latency Communications (URLLC), are considered. We focus on the network planning scenario, in which the radio processing resources and the data flows related to both NSs are subject to allocation in the xHaul network. Network optimization is performed by means of a scalable heuristic MaSCA-RA. The study reveals how the size and the bitrate of NSs affect the network performance in terms of the cost of involved processing resources.
Cited by 2