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About 2,589 papers for “Processor register”

Processor register error correction management

Pradip Bose · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 2023

Processor register protection management is disclosed. In embodiments, a method of processor register protection management can include determining a sensitive logical register for executable code generated by a compiler, generating an error-correction table identifying the sensitive logical register, and storing the error-correction table in a memory accessible by a processor. The processor can be configured to generate a duplicate register of the sensitive logical register identified by the error-correction table.

Cited by 0Open access

Register allocation for Intel processor graphics

Wei-Yu Chen, Guei-Yuan Lueh, Pratik Ashar et al. · 2018

Register allocation is a well-studied problem, but surprisingly little work has been published on assigning registers for GPU architectures. In this paper we present the register allocator in the production compiler for Intel HD and Iris Graphics. Intel GPUs feature a large byte-addressable register file organized into banks, an expressive instruction set that supports variable SIMD-sizes and divergent control flow, and high spill overhead due to relatively long memory latencies. These distinctive characteristics impose challenges for register allocation, as input programs may have arbitrarily-sized variables, partial updates, and complex control flow. Not only should the allocator make a program spill-free, but it must also reduce the number of register bank conflicts and anti-dependencies. Since compilation occurs in a JIT environment, the allocator also needs to incur little overhead.

Cited by 4

Mini Risc v processor ( ALU+ Register module)

Dr.k.R.Remya (project Head), Udhaya.R, Nithikkannan.J.S ,Ajaikumar.G ,Mukilan.R(Team) · Zenodo (CERN European Organization for Nuclear Research) · 2025

This paper presents the design and implementation of an 8-bit Mini RISC-V processor featuring an optimized Arithmetic Logic Unit (ALU) and a compact register block architecture suitable for low-power embedded applications. The processor is developed using modular HDL design principles to ensure scalability, reusability, and ease of verification. The ALU supports fundamental arithmetic and logical operations, including addition, subtraction, AND, OR, NOT, XOR, multiplication, and division, enabling a wide range of computational tasks. A 4-register, 8-bit register file is incorporated to provide efficient data storage and retrieval for instruction execution. The proposed architecture is simulated and verified using industry-standard EDA tools, ensuring correctness, functional stability, and timing reliability. Experimental results confirm the correct operation of all modules and demonstrate successful integration of the ALU and register block into a unified processor design. This lightweight and resource-efficient Mini RISC-V processor serves as an ideal solution for academic prototyping, teaching processors, digital design laboratories, and small-scale IoT applications.

Cited by 0Open access

Increasing processor performance through early register release

Oğuz Ergin, Deniz Balkan, Dmitry Ponomarev et al. · 2004

Modern superscalar microprocessors need sizable register files to support large number of in-flight instructions for exploiting ILP. An alternative to building large register files is to use smaller number of registers, but manage them more effectively. More efficient management of registers can also result in higher performance if the reduction of the register file size is not the goal. Traditional register file management mechanisms deallocate a physical register only when the next instruction with the same destination architectural register commits. We propose two complementary techniques for deallocating the register immediately after the instruction producing the register's value commits itself, without waiting for the commitment of the next instruction with the same destination. Our design relies on the use of a checkpointed register file (CRF), where a local shadow copy of each bitcell is used to temporarily save the early deallocated register values should they be needed to recover from branch mispredictions or to reconstruct the precise state after exceptions or interrupts. The proposed techniques outperform the previously proposed schemes for early deallocation of registers. For the register-constrained datapath configurations, our techniques result in up to 35% performance increase with 23.3% increase on the average across SPEC2000 benchmarks.

Cited by 62

Mini Risc v processor ( ALU+ Register module)

Dr.k.R.Remya, Udhaya.R,Nithikkanan.J.S,Ajaikumar.G,Mukilan.R · Zenodo (CERN European Organization for Nuclear Research) · 2025

This paper presents the design and implementation of an 8-bit Mini RISC-V processor featuring an optimized Arithmetic Logic Unit (ALU) and a compact register block architecture suitable for low-power embedded applications. The processor is developed using modular HDL design principles to ensure scalability, reusability, and ease of verification. The ALU supports fundamental arithmetic and logical operations, including addition, subtraction, AND, OR, NOT, XOR, multiplication, and division, enabling a wide range of computational tasks. A 4-register, 8-bit register file is incorporated to provide efficient data storage and retrieval for instruction execution. The proposed architecture is simulated and verified using industry-standard EDA tools, ensuring correctness, functional stability, and timing reliability. Experimental results confirm the correct operation of all modules and demonstrate successful integration of the ALU and register block into a unified processor design. This lightweight and resource-efficient Mini RISC-V processor serves as an ideal solution for academic prototyping, teaching processors, digital design laboratories, and small-scale IoT applications.

Cited by 0Open access

Mini Risc v processor ( ALU+ Register module)

Dr.k.R.Remya (project Head), Udhaya.R, Nithikkannan.J.S ,Ajaikumar.G ,Mukilan.R(Team) · Zenodo (CERN European Organization for Nuclear Research) · 2025

This paper presents the design and implementation of an 8-bit Mini RISC-V processor featuring an optimized Arithmetic Logic Unit (ALU) and a compact register block architecture suitable for low-power embedded applications. The processor is developed using modular HDL design principles to ensure scalability, reusability, and ease of verification. The ALU supports fundamental arithmetic and logical operations, including addition, subtraction, AND, OR, NOT, XOR, multiplication, and division, enabling a wide range of computational tasks. A 4-register, 8-bit register file is incorporated to provide efficient data storage and retrieval for instruction execution. The proposed architecture is simulated and verified using industry-standard EDA tools, ensuring correctness, functional stability, and timing reliability. Experimental results confirm the correct operation of all modules and demonstrate successful integration of the ALU and register block into a unified processor design. This lightweight and resource-efficient Mini RISC-V processor serves as an ideal solution for academic prototyping, teaching processors, digital design laboratories, and small-scale IoT applications.

Cited by 0Open access

Mini Risc v processor ( ALU+ Register module)

Dr.k.R.Remya, Udhaya.R,Nithikkanan.J.S,Ajaikumar.G,Mukilan.R · Zenodo (CERN European Organization for Nuclear Research) · 2025

This paper presents the design and implementation of an 8-bit Mini RISC-V processor featuring an optimized Arithmetic Logic Unit (ALU) and a compact register block architecture suitable for low-power embedded applications. The processor is developed using modular HDL design principles to ensure scalability, reusability, and ease of verification. The ALU supports fundamental arithmetic and logical operations, including addition, subtraction, AND, OR, NOT, XOR, multiplication, and division, enabling a wide range of computational tasks. A 4-register, 8-bit register file is incorporated to provide efficient data storage and retrieval for instruction execution. The proposed architecture is simulated and verified using industry-standard EDA tools, ensuring correctness, functional stability, and timing reliability. Experimental results confirm the correct operation of all modules and demonstrate successful integration of the ALU and register block into a unified processor design. This lightweight and resource-efficient Mini RISC-V processor serves as an ideal solution for academic prototyping, teaching processors, digital design laboratories, and small-scale IoT applications.

Cited by 0Open access

Integrating superscalar processor components to implement register caching

Matthew A. Postiff, David Greene, Steven Raasch et al. · 2001

A large logical register file is important to allow effective compiler transformations or to provide a windowed space of registers to allow fast function calls. Unfortunately, a large logical register file can be slow, particularly in the context of a wide-issue processor which requires an even larger physical register file, and many read and write ports. Previous work has suggested that a register cache can be used to address this problem. This paper proposes a new register caching mechanism in which a number of good features from previous approaches are combined with existing out-of-order processor hardware to implement a register cache for a large logical register file. It does so by separating the logical register file from the physical register file and using a modified form of register renaming to make the cache easy to implement. The physical register file in this configuration contains fewer entries than the logical register file and is designed so that the physical register file acts as a cache for the logical register file, which is the backing store. The tag information in this caching technique is kept in the register alias table and the physical register file. It is found that the caching mechanism improves IPC up to 20% over an un-cached large logical register file and has performance near to that of a logical register file that is both large and fast.

Cited by 36

Integrating Superscalar Processor Components to Implement Register Caching

Matthew Postiff David, David Greene, Steven Raasch et al. · 2001

A large logical register file is important to allow effective compiler transformations or to provide a windowed space of registers to allow fast function calls. Unfortunately, a large logical register file can be slow, particularly in the context of a wide-issue processor which requires an even larger physical register file, and many read and write ports. Previous work has suggested that a register cache can be used to address this problem. This paper proposes a new register caching mechanism in which a number of good features from previous approaches are combined with existing out-of-order processor hardware to implement a register cache for a large logical register file. It does so by separating the logical register file from the physical register file and using a modified form of register renaming to make the cache easy to implement. The physical register file in this configuration contains fewer entries than the logical register file and is designed so that the physical register file acts as a cache for the logical register file, which is the backing store. The tag information in this caching technique is kept in the register alias table and the physical register file. It is found that the caching mechanism improves IPC up to 20% over an un-cached large logical register file and has performance near to that of a logical register file that is both large and fast.

Cited by 0

Pseudo Vector Processor based on Register-Windowed Superscalar Pipeline

Nakazawa Kisaburo, Hiromitsu Kawabe · 1992

In this paper, we present a new architecture for highspeed pseudo vector processor based on a superscalar pipeline. Without using cache memory, the proposed architecture is able to overcome penalty of memory access latency by introducing register windows with register preloading and pipelined memory. One outstanding feature of the proposed architecture is that it is upward compatible with existing scalar architectures. Performance evaluation of the proposed architecture using the Livermore Loop Kernels shows over 6 times higher performance than a usual superscalar processor and 1.2 times higher performance than a hypothetical extended model with cache prefetching technique with a memory access latency of 20 CPU clock cycles. List vectors are also effectively handled in a similar architecture. 1. Introduction Motivation Over the past several years, technological and architectural advances have realized dramatic improvements in microprocessor performance with peak performances becoming...

Cited by 0

A quantum algorithm processor architecture based on register reordering

Masaki Nakanishi, Miki Matsuyama, Yumi Yokoo · 2014

Quantum computer simulators play an important role when we evaluate quantum algorithms. Quantum computation can be regarded as parallel computation in some sense, and thus, it is suitable to implement a simulator on a hardware, which can process a lot of operations in parallel. In this paper, we propose a processor architecture dedicated to simulating quantum algorithms. The proposed architecture is based on the register reordering method that shifts and swaps registers containing probability amplitudes so that the probability amplitudes of target basis states can be quickly selected. This reduces the number of large multiplexers and improves clock frequency. We implemented the processor on an FPGA. Experimental results show that the proposed processor has scalability in terms of the number of quantum bits, and can simulate quantum algorithms faster than software simulators.

Cited by 0

The Anatomy of the Register File in a Multiscalar Processor

Scott Breach Vijaykumar, Scott E. Breach, T. N. Vijaykumar et al. · 1994

This paper presents the operation of the register file in the Multiscalar architecture. The register file provides the appearance of a logically centralized register file, yet is implemented as physically decentralized register files, queues, and control logic in a Multiscalar processor. We address the key issues of storage, communication, and synchronization required for a successful design and discuss the complications that arise in the face of speculation. In particular, the hardware required to implement the register file is detailed, and software support to streamline the operation of the register file is described. Illustrative examples detailing important aspects of the operation of the register file and an evaluation of its effectiveness are provided. 1 Introduction The Multiscalar architecture is a novel architecture for exploiting instruction-level parallelism (ILP) [1] [2] that speculatively executes multiple operations in parallel, yet provides the semblance of sequential...

Cited by 0

An Optical-Holographic-Associative-Memory-Based Parallel Register Transfer Processor

George Eichmann, Andrew A. Kostrzewski, Dai Hyun Kim et al. · 1989

A combinatorial logic circuit is an interconnected array of logic gates. However, for various arithmetic operations, iterative sequential computation is needed. To furnish feedback, memory elements, such as flip-flops or registers must be utilized. With this feedback, the overall logic circuit is a finite-state sequential logic machine. The use of optics to perform fast combinatorial logic processing was suggested 1-3 . However, for the various proposed combinatorial logic elements the efficient feedback generation is an active research area. To generate a sequential logic circuit, a viable hybrid approach is to use optics for both fast parallel logic and interconnect and high-speed bit-addressable electronics for storage and feedback 1 . In this paper, a specific hybrid sequential computing module, where optical array processors that perform the combinatorial logic and interconnect operations, are sandwiched between high-speed electronic parallelly-addressed storage registers, is described. This hybrid system can sustain various fast optical register transfer micro-operations (ORTMOs), operations that are the most primitive operations required for an optical digital computer. This new system will be referred to as an optical register transfer processor (ORTP).

Cited by 0

Balancing register allocation across threads for a multithreaded network processor

Xiaotong Zhuang, Santosh Pande · 2004

Modern network processors employ multi-threading to allow concurrency amongst multiple packet processing tasks. We studied the properties of applications running on the network processors and observed that their imbalanced register requirements across different threads at different program points could lead to poor performance. Many times application needs demand some threads to be more performance critical than others and thus by controlling the register allocation across threads one could impact the performance of the threads and get the desired performance properties for concurrent threads. This prompts our work.Our register allocator aims to distribute available registers to different threads according to their needs. The compiler analyzes the register needs of each thread both at the point of a context switch as well as internally. Compiler then designates some registers as shared and some as private to each thread. Shared registers are allocated across all threads explicitly by the compiler. Values that are live across a context switch can not be kept in shared registers due to safety reasons; thus, only those live ranges that are internal to the context switch can be safely allocated to shared registers. Spill can cause a context switch. and thus, the problems of context switch and allocation are closely coupled and we propose a solution to this problem. The proposed interference graphs (GIG,BIG,IIG) distinguish variables that must use a thread's private registers from those that can use shared registers. We first estimate the register requirement bounds, then reduce from the upper bound gradually to achieve a good register balance among threads. To reduce the register needs, move insertions are inserted at program points that split the live ranges or the nodes on the interference graph. We show that the lower bound is reachable via live range splitting and is adequate for our benchmark programs for simultaneously assigning them on different threads. As our objective, the number of move instructions is minimized.Empirical results show that the compiler is able to effectively control the register allocation across threads by maximizing the number of shared registers. Speed-up for performance critical threads ranges from 18 to 24% whereas degradation for performance of non-critical threads ranges only from 1 to 4%.

Cited by 13

Enhancing boosting with semantic register in a superscalar processor (abstract)

Feipei Lai, Meng‐Chou Chang · 1992

IAS-S Supports boosting with “semantic register” and boosting boundary register to remove the dependences caused by conditional branches. In IAS-S, there is no dedicated shadow register file, and multiple levels of boosting is supported without multiple copies of register files. Any general-purpose register in IAS-S can be regarded as a sequential register or a shadow register flexibly. Furthermore, multi-way jump mechanism is combined with boosting to reduce the penalty due to frequent control transfers.

Cited by 0Open access