With An Stage, Kazuyuki Nakamura, Tsutomu Sasao et al. · 2005
Introduction RAMs and PLAs (Programmable Logic Array) are used for programmable logic devices that realize multiple-output combinational logic functions. However, when the number of inputs and/or outputs for the target function is large, these devices require excessive amounts of hardware. Thus, FPGAs (Field Programmable Gate Arrays) are often used. However, the area and delay for interconnections among logic cells are much larger than those for logic elements. Therefore the prediction of the performance of the FPGA is difficult without complete physical design. To solve these problems, an LUT cascade architecture that is composed of a serial connection of large-scale memories has been developed [1]. The LUT cascade uses relatively larger LUTs (1kb - 1Mb), and the interconnections between LUTs are limited to the adjacent cells in the cascade. This is quite different from the two-dimensional structure of FPGAs with smaller (16b - 64b) LUTs. The large area for the interconnections in an
Cited by 0
Cpld Board, Nagaraj Hediyal · 2012
Abstract: The design and development of Generic Complex Programmable Logic Device (CPLD) Board is to emphasis on the reduction of the overall design & development life cycle time of the products. Since the Programmable Logic Devices are very flexible, reconfigurable, the same board can be utilised in multiple system designs. These devices work at very low voltage, high speed and low power consumption. These features make the PLDs more versatile and increase the product reliability to the greater extent as the device count at the system level reduces enormously. Present board has on board Joint Testing Action Group (JTAG) interfaces for In-System programming purpose. This makes the board to be more flexible, in terms of design changes, up gradation and easy migration from one specification to another. The generic nature of the present work is demonstrated by implementing
Cited by 0
Microelectronics Journal · 1987
Cited by 0
Murali Seshadri Arthur Radun · Electric Machines & Power Systems · 2000
A resolver is a common motor shaft angular position sensor used in high-speed, high-performance motor control systems. A circuit is described that simulates such a resolver attached to a rotating electrical machine turning at constant speed in real time. The circuit simulates a resolver in that it produces the same outputs and uses the same inputs as an actual resolver. The circuit is a mixed analog and digital circuit that contains a Complex Programmable Logic Device (CPLD), flash memory chips, a Digital to Analog Converter, and Operational Amplifiers. The machine speed being simulated by the circuit is programmable. The design description and test results for this circuit are given.
Cited by 1
Tomasz Binkowski · SN Applied Sciences · 2019
Solar power plant system represents the clean energy generation systems which convert and deliver the large amounts of solar radiation energy to the grid. The main purpose of the study is to maximize the amount of energy delivered to the grid from the solar photovoltaic cells. The solar irradiance and the grid voltage are the complex and dynamic system and need the universal solution which can provide more power at high dynamics of changes in external, various conditions. This work focuses on investigations provided in detail for the fuzzy logic-based synchronization technique which significantly increases the energy efficiency of the photovoltaic system. The multi-photovoltaic system’s controller concept was elaborated and evaluated using the programmable logic device, particularly useful for power critical drives. The dynamic responses of photovoltaic system were measured, which refers to the start procedure, solar irradiance, grid frequency and phase angle change. The results of the photovoltaic system investigation are made to appoint the efficiency in relation to the standard solution. The proposed fuzzy logic-based synchronization method delivers more energy to the grid in dynamic states in relation to the standard phase-locked loop method. The normal operation of the photovoltaic system is the dynamic operation. Therefore, the solution described in work allows to increase the efficiency of solar farms.
Cited by 5Open access
E. Boemo, F. Barbero, J. Faura et al. · 1995
This paper resumes the development of an integrate tool for designing high-speed, real-time, FIR-filter circuits. The system is composed of programmable IC and an associate software for filter response analysis, synthesis of coefficients, and circuit programming. The architecture is highly regular, easily expandable and its control is distributed. The chip can be programmed by a PC or by using an EPROM. The prototypes have been fabricated using the CMOS 1.5µ Standard Cell of ES2. Moreover, some heuristics about multipliers upgrated to CMOS 1µ - Cadence DFWII are resumed.
Cited by 0
Faizal Arya Samman · Hasanuddin University Repository · 2017
This monograph book presents the design of digital fuzzy logic controller (FLC) processor and its implementation on a Complex Programmable Logic Device (CPLD). The FLC processor is modeled and designed using Very-High-Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL). The modeling, simulation and configration on the CPLD device is made using a software tools (integrated development environment ??? IDE) from Altera i.e. MAX+PLUS II. The book proposes the two-input single-output Programmable FLC with parallel architecture. The Programmable FLC can be programmed in terms of its 6-input membership functions and forms, 9-rule of the fuzzy \nimplication or inference, and its 3-output singleton consequences. Thus this FLC processor can be applied for wide-range control applications. The FLC circuit is \nimplemented on EPF10K70RC240-4, a FLEX10K CPLD device from Altera containing over 70,000 logic gates. The implementation result shows that it requires 98 % of total logic cells on the device. In-circuit testing presents that the FLC processor can be operated at clock frequency of 1.573 MHz. Using six-stage datapath pipeline latency, input-output operation delay time is about 3.1786 us.
Cited by 0
Songpol Ongwattanakul, Phaisit Chewputtanagul, David J. Jackson et al. · 2008
Common binary arithmetic operations such as addition/subtraction and multiplication suffer from O(n) carry propagation delay where n is the number of digits. Carry lookahead helps to improve the propagation delay to O(log n), but is bounded to a small number of digits due to the complexity of the circuit. A carry-free arithmetic operation can be achieved using a higher radix number system such as Quarternary Signed Digit (QSD). In QSD, each digit can be represented by a
Cited by 0
Z. R. Yan, Yizhou Liu, Guang Yao et al. · Physical Review Applied · 2021
The $m\phantom{\rule{0}{0ex}}e\phantom{\rule{0}{0ex}}m\phantom{\rule{0}{0ex}}o\phantom{\rule{0}{0ex}}r\phantom{\rule{0}{0ex}}y$ $w\phantom{\rule{0}{0ex}}a\phantom{\rule{0}{0ex}}l\phantom{\rule{0}{0ex}}l$, a bottleneck between storage and processor in the traditional von Neumann computing paradigm, has become increasingly serious with the rise of ``Big Data'', and there is strong interest in developing logic-in-memory computing architectures. The authors propose a skyrmion-based programmable logic device with complete Boolean logic functions, a feature that has remained elusive so far. This device can realize robust and programmable logic functions under solely electrical control, in the presence of both the inhomogeneities and thermal fluctuations that are are experimentally unavoidable. This result, then, suggests a path to overcoming the memory wall.
Cited by 62Open access
F. Ki, R. Bachireddy, Deog‐Kyoon Jeong et al. · 2002
An oxide-isolated programmable logic device (PLD) designed with emitter-coupled logic (ECL) performing beyond 200 MHz is described. This 100KH/100K compatible product is configurable, via standard fuse programming, to accept up to 20 inputs and have 8 outputs which are individually programmable to be combinatorial/registered, with/without feedback and active high/active low.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 0
Microprocessors and Microsystems · 1992
Cited by 0
Sun Yu-guo, Jin Chen · 2005
To meet the requirements of an embedded mechanical fault diagnosis system development, a fault tree implementation and dynamic modification method based on CPLD (Complex Programmable Logic Device) is investigated experimentally. The mechanism of fault tree logic calculation in the CPLD chip is presented. The fault logic tree is modeled by VHDL (VHSIC Hardware Description Language) and logic graphic, respectively. The effects of the bottom events on the logic result are simulated in Max + plus II platform. The fault tree logic is downloaded into the EPM7064SLC44-10 chip by ISP (In System Programmable) technology. And evaluated in terms of power consumption, system’s volume and design flexibility. The study results show that CPLD is suit to the fault tree’s construction, contributed by the chip’s outstanding ISP function and programmable logic function. And the fault tree logic synthesis and the chip resource optimization need to be further investigated.
Cited by 0
Zhiheng Cai (9663303), Yingqiang Fu (11607232), Zhili Qiu (11607235) et al. · Figshare · 2021
Accurate\ndiagnosis and precise and effective treatment are currently\nthe two magic weapons for dealing with cancer. However, a single marker\nis often associated with multiple cellular events, which is not conducive\nto accurate diagnosis, and overly mild treatment methods often make\nthe treatment effect unsatisfactory. In this paper, we construct a\nAu/Pd octopus nanoparticle–DNA nanomachine (Au/Pd ONP–DNA\nnanomachine) as a fully automatic diagnosis and treatment logic system.\nIn this system, multiple DNA components are targeting detection units,\nAu/Pd ONPs act as carriers, and Au/Pd ONPs with an 808 nm laser is\nthe treatment unit. In order to achieve the purpose of precise treatment,\nwe will detect two secondary markers under the premise of detecting\none major tumor marker. When all of the designated targets are detected\n(the logic system input is (1, 1, 1), and the output is (1, 1)), the\n808 nm laser can be programmed to automatically radiate tumors and\nperform photothermal therapy and photodynamic therapy. <i>In\nvivo</i> and <i>in vitro</i> experiments show that\nthis logic system not only can accurately identify tumor cells but\nalso has considerable therapeutic effects.
Cited by 0Open access
Zhiheng Cai, Yingqiang Fu, Zhili Qiu et al. · ACS Nano · 2021
Accurate diagnosis and precise and effective treatment are currently the two magic weapons for dealing with cancer. However, a single marker is often associated with multiple cellular events, which is not conducive to accurate diagnosis, and overly mild treatment methods often make the treatment effect unsatisfactory. In this paper, we construct a Au/Pd octopus nanoparticle-DNA nanomachine (Au/Pd ONP-DNA nanomachine) as a fully automatic diagnosis and treatment logic system. In this system, multiple DNA components are targeting detection units, Au/Pd ONPs act as carriers, and Au/Pd ONPs with an 808 nm laser is the treatment unit. In order to achieve the purpose of precise treatment, we will detect two secondary markers under the premise of detecting one major tumor marker. When all of the designated targets are detected (the logic system input is (1, 1, 1), and the output is (1, 1)), the 808 nm laser can be programmed to automatically radiate tumors and perform photothermal therapy and photodynamic therapy. <i>In vivo</i> and <i>in vitro</i> experiments show that this logic system not only can accurately identify tumor cells but also has considerable therapeutic effects.
Cited by 59
Alessandro Depari, Paolo Ferrari, Alessandra Flammini et al. · Electronics Letters · 2004
A simple and successful approach for signal frequency estimation is presented. If applied to multichannel measurements (i.e. resonant sensors arrays) this method allows smaller implementation compared to classical techniques (e.g. CET). A prototype has been developed to evaluate the algorithm and the measured data agree with predicted results.
Cited by 5
Grzegorz Śmigielski · MATEC Web of Conferences · 2022
The article presents a numerical control system of a multi-axis machine built using a programmable logic device.The system consists of PC, motor controller (based on FPGA), power stages and motors. The complete code of controller was written in the VHDL language and implementing in Xilinx Spartan 3 board. The PC program was created using LabVIEW.The logical and functional tests of the system have been carried out. The application of a programmable device enables its quick configuration according to the requirements set by the user.The main advantage of FPGA is the option to expand to following modules, such as the incremental encoder support module, PWM, FOC etc. In these applications, the advantage of the programmable system becomes visible, which due to its specifics, is built for parallel processing or generating signals.
Cited by 0Open access
Liangling Gu, Nanquan Zhou, Hongbing Li · Procedia Environmental Sciences · 2011
The design method of general integer and half-integer frequency divider circuits is introduced in this paper. It applies the module and parameterized idea, which can be realized under the FPGA developing platform. According to modifying the specific parameters, it can be applied to the different occasions. The experiment simulation and the result of the apparatus’ testing all get good effect. The generality of this design is good. It can be used into the designs of diverse digital circuit systems.
Cited by 4Open access
Gorontzi, Kay · DuEPublico (University of Duisburg-Essen) · 2003
Anwenderprogrammierbare Logikbausteine bieten eine einfache, kompakte und kostengünstige Möglichkeit zur Realisierung von Logikschaltungen im Umfeld von Microcontrollern. Besonders in elektronikfeindlichen Umgebungen, z. B. bei Temperaturen von 250 °C, waren sie jedoch bisher nicht erhältlich. Ausgehend vom aktuellen Stand der SIMOX-Technologie wird ein HTPAL als Vertreter einer neuen Klasse von Hochtemperaturbausteinen vorgestellt, dessen Eigenschaften in ähnlicher Kombination zuvor nicht verfügbar waren: ein grosser Temperaturbereich von -50 °C bis 250 °C und darüber, hohe Toleranz gegenüber ionisierender Strahlung, flexible und dauerhafte Programmierung durch den Endanwender. Der grosse Temperaturbereich resultiert aus dem Einsatz der SIMOX Technolgie mit einer besonders günstigen Schaltungstopologie und einem speziellen Layout für Hochtemperaturtransistoren. Die dauerhafte Programmierbarkeit wird durch die Verwendung eines neuen Transistortyps möglich, dem sog. TOXFET. Dieses einmal-programmierbare Element besteht aus einem SIMOX-Hochvolttransistor, dessen Drain-Anschluß durch ein Tunneloxid vom übrigen Transistor isoliert wurde.
Cited by 0Open access
Rajashree Narendra, ., Sudheer, M.L., Pande, D.C. · ePrints@Bangalore University (Bangalore University) · 2013
Complex electronics devices are becoming more sensitive to electrostatic discharge (ESD). These components are being developed with higher density (extra memory bits per unit volume) and are becoming faster (MHz, GHz, THz, etc.). These upgrades in technology do not come without a "technological price". By enhancing the products' performance to meet the users' demands and requirements, one drawback is the reduction in the ESD sensitivity voltage levels. Indirect and direct air/contact discharge test has been conducted on the ALS-SDA-CPLD/FPGA trainer kit linked to the digital to analog converter (DAC) module. The Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLD) are found to be very ESD sensitive. The FPGA 3s50 IC was affected during the contact discharge to the input pin. There was damage to the bond pad as well as the metal top layer was damaged. The DAC ICs were affected during the ESD discharge " one due to direct ESD effects and the other due to indirect ESD effects. There was dielectric breakdown damage observed in the CPLD 9572 IC.
Cited by 0
Jyotirmoy Pathak, Steve Douglass, D.-A. Vider et al. · 2003
A 20-ns, 600-mW, programmable logic device (PLD) using 0.8- mu m, two-layer metal, n-well CMOS EPROM technology is described. This PLD's architecture is optimized for asynchronous applications. It is a 28-pin device with 13 inputs, 12 I/Os, one V/sub CC/ and two V/sub SS/ pins. Each I/O pin has a macrocell which includes an input and an output register, and control muxes for output enable and feedback to the array. Product terms generate set, reset, and clock for each register independently. A product term input to the XOR gate can configure the D register into a JK, RS or T flip-flop. The sense amplifier is optimized for speed and power and is compensated for process, temperature, and pattern variations. The device uses substrate bias generator to improve performance and latchup immunity.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 0