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About 1,030 papers for “SDRAM”
2013
The migration from single data rate synchronous DRAM (SDR) to double data rate synchronous DRAM (DDR) memory is upon us. Although there are many similarities, DDR technology also provides notable
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Rizwana Begum, David Werner, Mark Hempstead et al. · 2015
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Mark Gurney · 2015
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Benny Åkesson, Kees Goossens · Embedded systems · 2011
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Interfacing Motorola’s Mpcxx · 2015
The Motorola MPC8xx integrated PowerPC™ microprocessor is designed for embedded solutions. The interface between this device and an SDRAM is done through one of the two UPMs (User Program-
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Mark Gurney · 2015
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Stratix Ii Devices · 2008
DDR SDRAM devices are widely used today for a broad range of applications, such as embedded processor systems, image processing, storage, communications and networking. In addition, the universal adoption of DDR SDRAM in PCs made DDR SDRAM memory a
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Alfonso Mascareñas González, Frédéric Boniol, Bouchebaba, Youcef et al. · Open Archive Toulouse Archive Ouverte (University of Toulouse) · 2021
The purpose of this paper is to describe a set of DDR3 SDRAM \ninterference estimation cost functions. The arbitration system of \nthe SDRAM controller heavily impact the interference analysis. \nIn this work, three arbitration are considered, corresponding to the situations where the accessed memory address belongs to the same block address, different memory banks and different rows. The aim of these functions is to estimate the instructions interference overhead may suffer when concurrently accessing these three logical addresses in a SDRAM saturation context. To develop these interference expressions, specific measurement systems, micro-benchmarks and theory on SDRAM controllers have been used.
Cited by 0Open access
2007
This application note describes a reference system that demonstrates the use of the Multi-CHannel (MCH) On-chip Peripheral Bus (OPB) Double Data Rate (DDR) Synchronous DRAM (SDRAM) controller in a MicroBlaze ™ processor system. Two MCH ports of the MCH OPB DDR SDRAM controller are connected to the cache ports of the MicroBlaze processor. The ports are configured with the Xilinx Cachelink (XCL) protocol which allows for efficient cacheline accesses by the processor. The OPB Central DMA controller is included in this system to generate OPB sequential address (burst) transactions. The software application provided with this reference system tests the capability of the MCH OPB DDR SDRAM core to handle cacheline accesses from the MicroBlaze processor and OPB burst transactions from the OPB Central DMA controller. The MCH OPB DDR SDRAM controller can be implemented on Virtex™-II Pro, Spartan™-3, and Virtex-4 FPGAs with boards that support DDR SDRAM. This application note describes how to set up MicroBlaze parameters for caching, the clocking structure for the MCH OPB DDR SDRAM, and parameters for OPB burst transactions from the OPB Central DMA controller. This reference system is targeted for the Xilinx SP305 Spartan-3
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Sven Goossens, Karthik Chandrasekar, Benny Åkesson et al. · Embedded systems · 2016
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2015
This technical note describes the proper interpretation and use of VOL and VOH specifi-cations for DDR3 SDRAM, including: • AC/DC conditions, including single-ended AC/DC output levels • AC timing and slew rate load, including the value of RON and equations for calculating
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V. Narasimharao · 2015
Abstract — This paper describes the implementation of AXI acquiescent DDR3 memory controller. It discusses the overall architecture of the DDR3 controller; it also discusses the AXI protocol operation. The DDR3 memory controller compares with DDR1 and DDR2 in performance wise. The design is simulated and synthesized on Xilinx ISE 13.2 successfully. Index Terms — AXI Interface, DDR3 memory, AXI protocol operation, AXI access Manager
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Jianghong Cui, Wencheng Guo, Jingli Yang · Modern Applied Science · 2008
With requirements of high data transmission efficiency, as the new SDRAM standard, DDR3 has gradually entered into our views. This article will analyze main functions of DDR3 and mainly compare DDR3 with DDR2.
Cited by 2Open access
Suchitra Shenoy, M. Madhushankara, Ribu Mathew et al. · Lecture notes in networks and systems · 2025
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Jian Qituo, Liansheng Liu, Yu Peng et al. · 2013
With the development of embedded systems, more and more applications require large and high speed memory. The FPGA-based solution also faces the same demand. Design and realization of an external storage with large capacity and high throughput in the FPGA-based embedded system is becoming a challenge. To satisfy the practical requirement, a DDR2 controller design is proposed, which efficiently and selectively integrates with the Altera DDR2 SDRAM High Performance Controller (HPC) module. Finally, the optimized DDR2 SDRAM controller based on Altera HPC is realized, and the goal that data accesses for DDR2 SDRAM with the ability of increase channel and relatively huge burst size is achieved. The optimized DDR2 controller has been implemented and verified in the Altera EP2SGX90E FPGA, and revealed a significant improvement in the performance compared with the individual HPC module. The experimental results show that this optimized DDR2 SDRAM controller demonstrates the properties of multichannel and high bandwidth memory access.
Cited by 3
Akesson, KB Benny, Goossens, KGW Kees, Ringhofer, M · TU/e Research Portal (Eindhoven University of Technology) · 2007
Memory requirements of intellectual property components (IP) in contemporary multi-processor systems-on-chip are increasing. Large high-speed external memories, such as DDR2 SDRAMs, are shared between a multitude of IPs to satisfy these requirements at a low cost per bit. However, SDRAMs have highly variable access times that depend on previous requests. This makes it difficult to accurately and analytically determine latencies and the useful bandwidth at design time, and hence to guarantee that hard real-time requirements are met. The main contribution of this paper is a memory controller design that provides a guaranteed minimum bandwidth and a maximum latency bound to the IPs. This is accomplished using a novel two-step approach to predictable SDRAM sharing. First, we define memory access groups, corresponding to precomputed sequences of SDRAM commands, with known efficiency and latency. Second, a predictable arbiter is used to schedule these groups dynamically at run-time, such that an allocated bandwidth and a maximum latency bound is guaranteed to the IPs. The approach is general and covers all generations of SDRAM. We present a modular implementation of our memory controller that is efficiently integrated into the network interface of a network-on-chip. The area of the implementation is cheap, and scales linearly with the number of IPs. An instance with six ports runs at 200 MHz and requires 0.042 mm2 in 0.13µm CMOS technology.
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2004
Many applications use single data rate (SDR) memory. However, as these applications become more demanding, designers need to find ways to improve performance without increasing cost. Over the years, DRAM
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Hong-Kai Chang, Youn-Long Lin · 2002
Multimedia, image processing and other signal processing applications often involve data stored in large arrays. Due to chip area limitation, arrays are typically assigned to off-chip memories, such as DRAM. This being the case, we try to optimize off-chip memory accesses to improve performance. We take the characteristics of the current mainstream SDRAM memory into account. We propose an algorithm to allocate arrays to different banks to increase the probability of utilizing SDRAM's multi-bank characteristic. Experimental results show significant improvement over traditional approaches.
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Edgar Lakis, Martin Schoeberl · 2013
For real-time systems we need to statically determine worst-case execution times (WCET) of tasks to proof the schedulability of the system. To enable static WCET analysis, the platform needs to be time-predictable. The platform includes the processor, the caches, the memory system, the operating system, and the application software itself. All those components need to be timing analyzable. Current computers use DRAM as a cost effective main memory. However, these DRAM chips have timing requirements that depend on former accesses and also need to be refreshed to retain their content. Standard memory controllers for DRAM memories are optimized to provide maximum bandwidth or throughput at the cost of variable latency for individual memory accesses. In this paper we present an SDRAM controller for realtime systems. The controller is optimized for the worst case and constant latency to provide a base of the memory hierarchy for time-predictable systems.
Cited by 11
Khaldon Hassan, Marcello Coppola · Lecture notes in electrical engineering · 2011
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