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About 10,000 papers for “Soft error”

Soft-error-analysis

Klampfl, Patrick Philip Bernd · TUGraz OPEN Library (Graz University of Technology) · 2022

Cited by 0Open access

Soft-threshold readout error.

Jonathan Timcheck (13970408), Jonathan Kadmon (13970411), Kwabena Boahen (13970414) et al. · Figshare · 2022

<p>(a) The soft-threshold and the delay create variations in the membrane potential dynamics <i>V</i><sub><i>i</i></sub>(<i>t</i>), which in turn create variations in the readout . When the membrane potentials (top, purple) surpass threshold, the neurons spike probabilistically, and the first-spike time is an exponential random variable with standard deviation . After a first spike, the number of spurious spikes that occur during the delay is a Poisson random variable, with standard deviation , and each spike inhibits the membrane potentials <i>V</i><sub><i>i</i></sub>(<i>t</i>) by 1 through recurrent connectivity (see the first paragraph of Results for recurrent connectivity). These variations in spike-timing and spurious spikes carry through to the readout (bottom, blue). Note that since the network input is constant, the readout encoding this input should produce a constant output as closely as possible; however, these variations instead increase the deviation (light blue shaded) from the mean readout (black horizontal line). (b) Readout error as a function of the mean number of spurious spikes λ and the delay <i>δ</i>. Top: for three different values of delay (blue, red, purple), λ is varied in computer simulations (N = 32, dots) and <a href="http://www.ploscompbiol.org/article/info:doi/10.1371/journal.pcbi.1010593#pcbi.1010593.e065" target="_blank">Eq 10</a> (solid curves), revealing both the U-shaped dependence of the readout error <i>σ</i><sub><i>readout</i></sub> and an excellent match between theory and experiment. Bottom: the optimal readout error (black) and the associated optimal λ* increase as a function of delay <i>δ</i> according to Eqs <a href="http://www.ploscompbiol.org/article/info:doi/10.1371/journal.pcbi.1010593#pcbi.1010593.e070" target="_blank">12</a> and <a href="http://www.ploscompbiol.org/article/info:doi/10.1371/journal.pcbi.1010593#pcbi.1010593.e069" target="_blank">11</a>.</p>

Cited by 0Open access

Soft Error Rate Measurements

Dr Frank Schlaphof, Dr Carlo Cazzaniga · Science and Technology Facilities Council · 2018

Soft error rate measurements will be conducted by means of high energy neutron irradiation on electronic devices.

Cited by 0Open access

Frequency Dependency of Soft Error Rates Based on Dynamic Soft Error Measurements

Haruto Sugisaki, Ryuichi Nakajima, Shotaro Sugitani et al. · 2023

We conducted a study on the frequency dependence analysis of soft error rates using flip-flops (FF) and inverters. The measurement circuit consists of scan FFs and inverters. By irradiating the circuit with alpha particles while the clock was running, the soft error rates were measured. The results showed that soft errors caused by inverters were almost negligible. On the other hand, the soft errors caused by FFs decreased as the operating frequency increased. The time window when the FF cannot capture its input until the rising edge of the clock is fixed at any clock frequency. As a result, as the operating frequency increases, the ratio of where errors are not captured to time in one cycle becomes larger.

Cited by 5

Soft Error Resilient System Design through Error Correction.

Subhasish Mitra, Ming Zhang, N. Seifert et al. · 2006

This paper presents an overview of the Built-In Soft Error Resilience (BISER) technique for correcting soft errors in latches, flip-flops and combinational logic. The BISER technique enables more than an order of magnitude reduction in chip-level error soft rate with minimal area impact, 6-10 % chip-level power impact, and 1-5% performance impact (depending on whether combinational logic error correction is implemented or not). In comparison, several classical error-detection techniques introduce 40-100 % power, performance and area overheads, and require significant efforts for designing and validating corresponding recovery mechanisms. Design trade-offs associated with the BISER technique and other existing soft error protection

Cited by 0

SIMD-based soft error detection

Zhi Chen, Alexandru Nicolau, Alexander V. Veidenbaum · 2016

Soft error rates in processors have been increasing with decreasing feature size and larger chips. Software-only solutions have been proposed to deal with this problem, for instance via instruction duplication. However, this leads to significant overheads in performance and energy. This paper proposes a novel approach to instruction duplication, which exploits the redundancy within SIMD instructions. The proposed solution is implemented in the LLVM compiler. Execution of a set of compiled C/C++ benchmarks shows that the SIMD based instruction duplication introduces a 32% performance and an 25% energy overheads, respectively, over the baseline. The performance and energy overheads of the state-of-the-art scalar instruction duplication approach are, on average, 111% and 114%, repsectively.

Cited by 13

Design for soft error mitigation

M. Nicolaidis · IEEE Transactions on Device and Materials Reliability · 2005

In nanometric technologies, circuits are increasingly sensitive to various kinds of perturbations. Soft errors, a concern for space applications in the past, became a reliability issue at ground level. Alpha particles and atmospheric neutrons induce single-event upsets (SEU), affecting memory cells, latches, and flip-flops, and single-event transients (SET), initiated in the combinational logic and captured by the latches and flip-flops associated to the outputs of this logic. To face this challenge, a designer must dispose a variety of soft error mitigation schemes adapted to various circuit structures, design architectures, and design constraints. In this paper, we describe various SEU and SET mitigation schemes that could help the designer meet her or his goals.

Cited by 333

Error Correction For Soft Errors

T Dhanushya, T. Latha · Journal of Electrical & Electronic Systems · 2018

Radiation induced soft errors are susceptible to most of the electronic products with the development of CMOS technology. A particle striking on any of the electronic products can produce soft errors that can be either single event upset or single event transient. There are various techniques such as FERST, BISER, TMR, DMR, DICE, SEC-DED, DEC-TED, EDAC, PARSHIELD, and STEM for soft error elimination. But these techniques do not provide self-checking capability, and has high area, output corruption. Soft Error and Timing error Tolerant Flip Flop (SETTOFF) is used to conquer these drawbacks. The self-checking is provided at the transition detection part. SETTOFF is designed for normal operation and fault operation. This has higher area overhead than BISER. So BISER by means of self-checking capability has been proposed to conquer the limitations by reducing the area. BISER by means of self-checking can yield better results with reduced area overhead, power and delay compared to SETTOFF architecture and BISER. The architecture is implemented using SPICE and simulation waveforms are obtained.

Cited by 2

Register file soft error recovery

Bruce Fleischer · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 2023

Register file soft error recovery including a system that includes a first register file and a second register file that mirrors the first register file. The system also includes an arithmetic pipeline for receiving data read from the first register file, and error detection circuitry to detect whether the data read from the first register file includes corrupted data. The system further includes error recovery circuitry to insert an error recovery instruction into the arithmetic pipeline in response to detecting the corrupted data. The inserted error recovery instruction replaces the corrupted data in the first register file with a copy of the data from the second register file.

Cited by 0Open access

Asymmetric soft-error resistant memory

Buehler, Martin G., Perlman, Marvin · NASA Technical Reports Server (NASA)

A memory system is provided, of the type that includes an error-correcting circuit that detects and corrects, that more efficiently utilizes the capacity of a memory formed of groups of binary cells whose states can be inadvertently switched by ionizing radiation. Each memory cell has an asymmetric geometry, so that ionizing radiation causes a significantly greater probability of errors in one state than in the opposite state (e.g., an erroneous switch from '1' to '0' is far more likely than a switch from '0' to'1'. An asymmetric error correcting coding circuit can be used with the asymmetric memory cells, which requires fewer bits than an efficient symmetric error correcting code.

Cited by 0Open access