Skip to content
Free planNo credit card requiredStart writing
AI for Research home
AI for Research home
Dashboard
Sign inGet started

Search 250 million research papers

Read the abstract, see who wrote it and who cites it, and get the citation in APA, MLA, Chicago or Harvard.

About 2,099 papers for “Static timing analysis”

Static Timing Analysis

Sneh Saurabh · 2023

Chip designing is a complex task that requires an in-depth understanding of VLSI design flow, skills to employ sophisticated design tools, and keeping pace with the bleeding-edge semiconductor technologies. This lucid textbook is focused on fulfilling these requirements for students, as well as a refresher for professionals in the industry. It helps the user develop a holistic view of the design flow through a well-sequenced set of chapters on logic synthesis, verification, physical design, and testing. Illustrations and pictorial representations have been used liberally to simplify the explanation. Additionally, each chapter has a set of activities that can be performed using freely available tools and provide hands-on experience with the design tools. Review questions and problems are given at the end of each chapter to revise the concepts. Recent trends and references are listed at the end of each chapter for further reading.

Cited by 1

Static Timing Analysis

Sachin S. Sapatnekar · 2018

Static timing analysis (STA) plays a vital role in facilitating the fast and reasonably accurate measurement of circuit timing. This chapter provides an overview some of the most prominent techniques for STA. It outlines issues related to Statistical Static Timing Analysis, a procedure that is becoming increasingly necessary to handle the complexities of process and environmental variations in integrated circuits. The chapter presents techniques that are used for the STA of digital combinational circuits. The word “static” alludes to the fact that this timing analysis is carried out in an input-independent manner, and purports to find the worst-case delay of the circuit over all possible input combinations. Unlike interdie variations, whose effects can be captured by a small number of STA runs at the process corners, a more sophisticated approach is called for in dealing with intradie variations. This requires an extension of traditional STA techniques to move beyond their deterministic nature.

Cited by 3

Voltage-Aware Static Timing Analysis

D. Kouroussis, Rubil Ahmadi, Farid N. Najm · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2006

Static timing analysis (STA) techniques allow a designer to check the timing of a circuit at different process corners, which typically include corner values of the supply voltages as well. Traditionally, however, this analysis only considers cases where the supplies are either all low or all high. As will be demonstrated, this may not yield the true maximum delay of a circuit because it neglects the possible mismatch between the supplies of successive gates on a path. A new methodology for timing analysis is proposed, where, in a first step, the critical paths of a circuit are identified under an assumption that all the supply nodes are independent of one another, thus allowing for mismatch between the supplies. Then, given these critical paths, the authors incorporate into the analysis the relationships between the supply node voltages by considering the power grid that they are tied to, and refine the worst case time delay values on a per-critical-path basis. This refinement is posed as a sequence of optimization problems where the operation of the circuit is abstracted in terms of current constraints. The authors present their technique and report on the implementation results using benchmark circuits tied to a number of test-case power grids

Cited by 7

Timing Yield Estimation Using Statistical Static Timing Analysis

Min Pan, Chris Chu, Haidong Zhou · 2005

As process variations become a significant problem in deep sub-micron technology, a shift from deterministic static timing analysis to statistical static timing analysis for high-performance circuit designs could reduce the excessive conservatism that is built into current timing design methods. We address the timing yield problem for sequential circuits and propose a statistical approach to handle it. We consider the spatial and path reconvergence correlations between path delays, set-up time and hold time constraints, and clock skew due to process variations. We propose a method to get the timing yield based on the delay distributions of register-to-register paths in the circuit On average, the timing yield results obtained by our approach have average errors of less than 1.0% in comparison with Monte Carlo simulation. Experimental results show that shortest path variations and clock skew due to process variations have considerable impact on circuit timing, which could bias the timing yield results. In addition, the correlation between longest and shortest path delays is not significant.

Cited by 21

Relational Cache Analysis for Static Timing Analysis

Sebastian Hahn, Daniel Grund · 2012

Static cache analysis is an indispensable part of static timing analysis, which is employed to verify the timing behaviour of programs in safety-critical real-time systems. State-of-the-art cache analyses classify memory references as `always hit', `always miss', or `unknown'. To do so, they rely on a preceding address analysis that tries to determine the referenced addresses. If a referenced address is not determined precisely, however, those cache analyses cannot predict this reference as hit or miss. On top of that, information about other cache contents is lost upon such references. We present a novel approach to static cache analysis that alleviates the dependency on precise address analysis. Instead of having to argue about concrete addresses, we only need to argue about relations between referenced addresses, e.g. `accesses same memory block' or `maps to different cache set'. Such relations can be determined by congruence analyses, without precise knowledge about the actual addresses. The subsequent cache analysis then only relies on relations to infer cache information and to classify references. One advantage of this approach is that hits can be predicted for references with imprecisely determined addresses, even if there is no information about accessed addresses. In particular, this enables the prediction of hits for references whose addresses depend on an unknown stack pointer or even depend on the program input. Relational cache analysis is always at least as precise as the corresponding state-of-the-art cache analysis. Furthermore, we demonstrate significant improvements for three classes of program constructs.

Cited by 16

On Hierarchical Statistical Static Timing Analysis

Li, Bing, Chen, Ning, Schmidt, Manuel et al. · arXiv (Cornell University) · 2017

Statistical static timing analysis deals with the increasing variations in manufacturing processes to reduce the pessimism in the worst case timing analysis. Because of the correlation between delays of circuit components, timing model generation and hierarchical timing analysis face more challenges than in static timing analysis. In this paper, a novel method to generate timing models for combinational circuits considering variations is proposed. The resulting timing models have accurate input-output delays and are about 80% smaller than the original circuits. Additionally, an accurate hierarchical timing analysis method at design level using pre-characterized timing models is proposed. This method incorporates the correlation between modules by replacing independent random variables to improve timing accuracy. Experimental results show that the correlation between modules strongly affects the delay distribution of the hierarchical design and the proposed method has good accuracy compared with Monte Carlo simulation, but is faster by three orders of magnitude.

Cited by 0Open access

Statistical Static Timing Analysis and Optimization

Narendra Shenoy · 2008

Circuit design needs to account for variability in process and operating conditions in order to manufacture a reasonable ratio of functional chips to total fabricated chips. This ratio is often termed as the “yield ” of a design. Traditionally, this has been achieved by providing margins for the worst-case scenario during the design process. Unfortunately this makes an implicit assumption that there is a single worst-case assignment to process parameters and operating conditions. Secondly, this can lead to severe over design in terms of area and power. As technology scales, the effect of variability on circuit behavior increases. This project aims to 1. Develop fast statistical timing analysis technology for use during optimization 2. Define a timing yield metric and design an optimization strategy to improve the timing yield 3. Compare timing yield in the traditional worst-case design methodology to a design methodology that accommodates variability Details The statistical models for gate delays are built by examining the delay behavior of the

Cited by 0

Refined statistical static timing analysis through

Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir · 2006

Statistical static timing analysis (SSTA) has been a popular research topic in recent years. A fundamental issue with applying SSTA in practice today is the lack of reliable and efficient statistical timing models (STM). Among many types of parameters required to be carefully modeled in an STM, spatial delay correlations are recognized as having significant impact on SSTA results. In this work, we assume that exact modeling of spatial delay correlations is quite difficult, and propose an experimental methodology to resolve this issue. The modeling accuracy requirement is relaxed by allowing SSTA to impose upper bounds and lower bounds on the delay correlations. These bounds can then be refined through learning the actual delay correlations from path delay testing on silicon. We utilize SSTA as the platform for learning and propose a Bayesian approach for learning spatial delay correlations. The effectiveness of the proposed methodology is illustrated through experiments on benchmark circuits.

Cited by 8

Static timing analysis in VLSI design

Zhou, Shuo · eScholarship (California Digital Library) · 2006

The increasing complexity of digital designs and the requirement of timing measurements in various design stages make static timing analysis critical. Each design stage utilizes static timing analysis to evaluate the system performance, and then optimizes the design accordingly. An accurate and efficient timing analysis package is crucial for the success of the whole design process. We studied three important problems in static timing analysis: false paths, multi-cycle paths, and hierarchical timing analysis. Static timing analysis should deal with false paths and multi-cycle paths to produce accurate timings. Previous published works focused on dealing with false paths in static timing analysis. There are several approaches, such as labeling algorithm and node-splitting approach, using tags to label and eliminate false path timings. A large number of tags need to be created and propagated. Thus, the efficiency is deteriorated. For hierarchical timing analysis, timing analysis iteratively performed on flatten circuits suffers from low efficiency because of increasing design complexity. Inspired by the gap between challenges and current sub-optimal solutions, we proposed three new techniques: 1. A two-direction propagation is proposed which minimizes the number of tagged false path timings using a biclique covering approach. We proved that all the non-false paths are covered and all the false paths are removed. A polynomial heuristic to perform the biclique covering minimization in minimal degree order is also introduced. 2. A framework unified processing false paths and multi-cycle paths is proposed which expands the tag- based approach for false paths to cover multi-cycle paths. Following the biclique covering approach for false paths, we devise time shifting for multi-cycle paths to improve the efficiency. We prove that the unified framework produces accurate timings. 3. An abstract timing model reduction technique is proposed for hierarchical timing analysis. We introduce an iterative biclique-star replacement technique to minimize the abstract timing model, thus improving the efficiency. Combined the techniques proposed above, we provide an accurate and efficient static timing analysis package, which can be used in hierarchical design methodology

Cited by 0Open access

Temperature aware statistical static timing analysis

Artem Rogachev, Lu Wan, Deming Chen · 2011

With technology scaling, the variability of device parameters continues to increase. This impacts both the performance and the temperature profile of the die turning them into a statistical distribution. To the best of our knowledge, no one has considered the impact of the statistical thermal profile during statistical analysis of the propagation delay. We present a statistical static timing analysis (SSTA) tool which considers this interdependence and produces accurate timing estimation. Our average errors for mean and standard deviation are 0.95% and 3.5% respectively when compared against Monte Carlo simulation. This is a significant improvement over SSTA that assumes a deterministic power profile, whose mean and SD errors are 3.7% and 20.9% respectively. However, when considering >;90% performance yield, our algorithm's accuracy improvement was not as significant when compared to the deterministic power case. Thus, if one is concerned with the runtime, a reasonable estimate of the performance yield can be obtained by assuming nominal power. Nevertheless, a full statistical analysis is necessary to achieve maximum accuracy.

Cited by 7

Cyclic Timing Path Evaluation Using Commercial Static Timing Analysis Algorithms

Mackenzie J. Wibbels, Baudouin Chauviere, Kenneth S. Stevens · 2023

Many circuit design methodologies employ combinational logic with feedback to realize logic functions. Obtaining accurate delay values for cyclic timing paths is an impediment to the adoption of these technologies. Static timing analysis (STA) algorithms are the standard for digital timing validation but require that timing arcs form directed acyclic graphs. STA algorithms can be used to evaluate cyclic timing paths with a loss in accuracy by cutting cycles into acyclic segments and summing each segment in a cyclic timing path. This paper reports on sources of error in using static timing analysis to evaluate acyclic timing segments of cyclic timing paths, and shows that using timing segments to evaluate cyclic timing paths with STA can lead to both overly pessimistic and incorrect delay calculations. A method is presented to accurately evaluate segmented cyclic timing paths and detect drafting conditions using STA tools. The algorithm is executed on a number of common cyclic circuits and has been shown to accurately evaluate segmented cyclic path delays compared to fully unrolled circuit paths for different operating conditions, fanout loads, and timing path cuts.

Cited by 1

Static timing analysis considering power supply variations

Sanjay Pant, David Blaauw · 2005

Power supply integrity verification has become a key concern in high performance designs. In deep submicron technologies, power supply noise can significantly increase the circuit delay and lead to performance failures. Traditional static timing analysis which applies worst-case voltage margins to compute circuit delay leads to a very conservative analysis because the worst-case drop is localized to a small area of the die. In this paper, we propose a new approach for analyzing the impact of power supply variations on circuit delay. The circuit delay maximization problem is formulated as a constrained non-linear optimization problem which takes both IR and Ldi/dt drops into account The proposed approach does not require apriori knowledge of critical paths in the circuit and can be effectively incorporated in an existing static timing analysis framework. The proposed method has been implemented and tested on ISCAS85 benchmark circuits and compared with the traditional methods for computing worst-case circuit delay under supply variations.

Cited by 23