Skip to content
Free planNo credit card requiredStart writing
AI for Research home
AI for Research home
Dashboard
Sign inGet started

Search 250 million research papers

Read the abstract, see who wrote it and who cites it, and get the citation in APA, MLA, Chicago or Harvard.

About 2,671 papers for “Systolic array”

Systolic convolution array

Joseph A. Simons · Electronics Letters · 1983

A systolic convolution array is presented, which has the minimum possible number of register stages, fixed fan-out, fan-in and response time, and which accepts a single input stream at the clock rate.

Cited by 3

Systolic Array Processors

M. Vai, Huy Thong Nguyen, Preston A. Jackson et al. · 2018

This chapter discusses the design and application of systolic arrays. It presents the development of a beamformer to demonstrate an intuitive design process of an application-specific processor. The chapter introduces a number of high performance processor design examples, including a real-time fast Fourier transform, a high performance QR decomposition for adaptive beamforming, and a very-large-scale integration bit-level systolic array finite impulse response filter. A systematic approach for the design and analysis of systolic arrays is explained, and a number of high performance processor design examples are provided. A systolic array consists of an arrangement of processing elements (PEs), optimally designed and interconnected to explore parallel processing and pipelining in the desired signal processing task. A straightforward implementation of a beamformer is, therefore, to provide four beamformer modules to form four concurrent beams in parallel. Since the sensor outputs are used in different pipeline stages, apparently buffers are needed to hold the samples until they are used in the pipelined computation.

Cited by 1

Multiple voting systolic array

Hideki Mori, J. Kambara · 2002

A model of the multiple voting systolic array is proposed. The proposed fault tolerant technique uses majority decision by voting, without reconfiguration. As an example, a DFT (discrete Fourier transform) implementation of a triple voting systolic array is presented. It is shown that area redundancy is small and dynamic fault recovery is possible. It is believed that proposed fault-tolerant architecture is suitable for WSI (wafer-scale integration) processors.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 2

QCA Systolic array design

O'Neill, Maire, Lu, Liang, Liu, Weiqiang et al. · Research Portal (Queen's University Belfast) · 2013

Cited by 0

Systolic Array Adaptive Beamforming

N.L. Owsley · 1987

Abstract : A computing architecture which reflects the specific requirements of an optimum adaptive space-time array processor is discussed. Specifically, a frequency domain implementation of the minimum variance distortionless response (MVDR) beamformer is described. Two systolic computing arrays are presented which implement respectively a rank one update of the Cholesky factor for a spatial sensor array cross-spectral covariance matrix and the solution of a set of linear equations for the optimum array matrix filter beamformer operation. The theoretical performance of the MVDR beamformer is reviewed. Finally, an array partitioning approach permits the application of systolic MVDR beamforming to arrays with very large numbers of sensors is proposed. Two sub-optimum MVDR processes are considered which exhibit nearly optimum performance at high interference-to-noise ratios.

Cited by 15

Optical Systolic Array Processors.

Caulfield,H J, Israel,Scott, Putnam,Roger · Defense Technical Information Center (DTIC) · 1985

Multiplication with 16 bit accuracy can be accomplished by optical means and is competitive and superior in speed to fully electronic devices if a sum-of-products algorithm is being implemented. The advantage of optics is not in the multiply function where electronic multipliers will be generally faster due to the extra analog-to-digital converters needed in the optical device. The optics advantage appears when many of the resulting numerical products need to be added which is accomplished by integrating sequential light pulses onto one detector. The bottleneck for digital addition is the arithmetic carry terms which are evaluated sequentially. We also present and analyze a threshold logic analog-to-digital converter intended for the optical multiplier which demonstrates increased speed over a successive approximation A/D without the complexity of a flash converter. We also present a significant step which is the sideways summer. The sideways summer greatly reduces the time required for the one step of electronic addition which is part of the digital-multiplication by analog-convolution algorithm. This electronic addition is needed to convert the resulting mixed binary form of the output into a normal binary number. Keywords include: Optical signal processing, and Computer architecture.

Cited by 0

Reconfigurable Systolic Array Implementation of

M Van Pee, Pramod P. Khargonekar, E. Bruce Lee et al. · 1986

B( zl, z2) = 1 - z2 + 0.22; - 0.5~~ + 0.8~~~~ Abstract -In this correspondence, we present a new reconfigurable implementation structure for quadratic digital filters using systolic arrays. The structure is based on matrix decomposition realizations and exhibits high parallelism, great modularity, and regularity. It is flexible enough to accommodate any quadratic filter of a given order and rank, just by opening a number of switches and tuning a set of parameters at each active module.

Cited by 0

Systolic Array Placement on FPGAs

Hailiang Hu, Donghao Fang, Wuxi Li et al. · 2023

Systolic array designs have regained popularity in recent years, particularly for their applications in accelerating CNN (Convolutional Neural Network) computing in hardware, including on FPGAs. However, existing FPGA layout techniques are primarily designed for general-purpose applications and have not fully leveraged the regularity of systolic arrays to enhance solution quality. This paper presents a new algorithmic approach for systolic array placement on FPGAs. Our approach enables 23% – 25% wirelength reduction for CNN circuits compared to an industrial tool and state-of-the-art academic methods. Moreover, it usually leads to significantly reduced routing resource utilization, accelerated placement runtime and improved timing performance.

Cited by 7

Dynamically Reconfigurable Systolic Array Accelerator

Dasu, Aravind, Barnes, Robert · NASA Technical Reports Server (NASA)

A polymorphic systolic array framework has been developed that works in conjunction with an embedded microprocessor on a field-programmable gate array (FPGA), which allows for dynamic and complimentary scaling of acceleration levels of two algorithms active concurrently on the FPGA. Use is made of systolic arrays and a hardware-software co-design to obtain an efficient multi-application acceleration system. The flexible and simple framework allows hosting of a broader range of algorithms, and is extendable to more complex applications in the area of aerospace embedded systems. FPGA chips can be responsive to realtime demands for changing applications needs, but only if the electronic fabric can respond fast enough. This systolic array framework allows for rapid partial and dynamic reconfiguration of the chip in response to the real-time needs of scalability, and adaptability of executables.

Cited by 0Open access

Dynamically Reconfigurable Systolic Array Accelorators

Barnes, Robert C., Dasu, Aravind · NASA STI Repository (National Aeronautics and Space Administration)

A polymorphic systolic array framework that works in conjunction with an embedded microprocessor on an FPGA, that allows for dynamic and complimentary scaling of acceleration levels of two algorithms active concurrently on the FPGA. Use is made of systolic arrays and hardware-software co-design to obtain an efficient multi-application acceleration system. The flexible and simple framework allows hosting of a broader range of algorithms and extendable to more complex applications in the area of aerospace embedded systems.

Cited by 0Open access

A Systolic Array Programming Language

Ping-Sheng Tseng · 2005

The author gives an overview of the Warp systolic array and describes the AL language and its implementation for the Warp machine. AL is a sequential programming language extended with the DARRAY data structure and DO looping construct to guide the compiler to generate efficient parallel code. The author has implemented an AL compiler for the Warp machine and has been using AL to program matrix computation applications. Examples of LU decomposition, QR decomposition, and singular value decomposition (SVD) are given to illustrate the use of AL. More than 27 MFLOPS (out of 100 MFLOPS peak) on matrices of order 300 were achieved for these applications. >

Cited by 8

Systolic Array Matrix Multiplication Accelerator

Alexandru Puşcaşu, Cătălin Bogdan Ciobanu, Octavian Buiu · Zenodo (CERN European Organization for Nuclear Research) · 2024

Systolic arrays are a simple solution to accelerate matrix multiplication. Matrix multiplication is a common operation used in artificial intelligence. We designed a loosely-coupled matrix multiplier with a 2D systolic array. The accelerator is configured with matrices parameters. The host raises a start flag to start an operation and when is completed another flag is raised by the accelerator. The accelerator has dedicated memory interfaces. The accelerator was designed in Sytem Verilog. The design was synthesized targeting an AMD/Xilinx VCU128 FPGA to measure the area utilization for various 2D systolic array dimensions. Another tests counted the clock cycles for the matrix multiplication. To reduce the total operation time, we proposed a parallel data flow. The design works on different clock domains: for the interfaces and the internal logic. Our experimental results suggest that our accelerator is up to 3.1X faster for a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$8\times 8$</tex> Systolic Array and up to 145.5X faster for a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$64\times 64$</tex> Systolic Array compared to baseline RISC- V processor.

Cited by 3Open access