Timing Attack
François Koeune · 2025
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About 2,884 papers for “Timing attack”
François Koeune · 2025
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François Koeune · 2023
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François Koeune · 2011
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Andrew C. Hampson II Hampson · Zenodo (CERN European Organization for Nuclear Research) · 2026
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Andrew C. Hampson II Hampson · Zenodo (CERN European Organization for Nuclear Research) · 2026
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Howard Heys · 1998
In this paper, we examine the application of a timing attack to the RC5 symmetric block cipher. The analysis is motivated by the possibility that a naive implementation of RC5 could result in the data-dependent rotations taking a time that is a function of the data. Such implementations are possible, for example, in a digital hardware or 8-bit microcontroller environment. Based on the assumption that accurate timing measurements are available for individual encryptions, the methodology of deriving key bits using timing information from a set of ciphertexts is outlined and it is shown that, for the nominal version of RC5, with only about 2000 ciphertexts and their associated timings, the cryptanalysis can be applied to determine 5 bits of the last half-round subkey with high probability. Further, using a set of about 64000 random ciphertexts, the attack can be applied to determine the entire subkey of the last half-round with high probability and, if 10^6 random ciphertexts and thei...
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Francois Koeune, Francois Koeune, Jean-Jacques Quisquater et al. · 1999
This paper describes a timing attack against the AES candidate Rijndael. We show how a careless implementation can be broken with some thousands measures per key byte, provided a very limited knowledge of the implementation. 2 Brief description of Rijndael
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I. Peterson · Science News · 1995
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Digital Repository Service (Northeastern University)
Graphics Processing Units (GPUs) have become mainstream parallel computing devices. They are deployed on diverse platforms, and an increasing number of applications have been moved to GPUs to exploit their massive parallel computational resources. GPUs are starting to be used for security services, where high-volume data is encrypted to ensure integrity and confidentiality. However, the security of GPUs has only begun to receive attention. Issues, such as side-channel vulnerability, have not been addressed. \n\n The goal of this paper is to evaluate the side-channel security of GPUs and demonstrate a complete AES (Advanced Encryption Standard) key recovery using known ciphertext through a timing channel. To the best of our knowledge, this is the first work that clearly demonstrates the vulnerability of a commercial GPU architecture to side-channel timing attacks. Specifically, for AES-128, we have been able to recover all key bytes utilizing a timing side channel in under 30 minutes.
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Senyang Huang, Rui Qi Sim, Chitchanok Chuengsatiansup et al. · IACR Transactions on Cryptographic Hardware and Embedded Systems · 2023
In this paper, we present the first chosen-ciphertext (CC) cache-timing attacks on the reference implementation of HQC. We build a cache-timing based distinguisher for implementing a plaintext-checking (PC) oracle. The PC oracle uses side-channel information to check if a given ciphertext decrypts to a given message. This is done by identifying a vulnerability during the generating process of two vectors in the reference implementation of HQC. We also propose a new method of using PC oracles for chosen-ciphertext side-channel attacks against HQC, which may have independent interest.We show a general proof-of-concept attack, where we use the Flush+Reload technique and also derive, in more detail, a practical attack on an HQC execution on Intel SGX, where the Prime+Probe technique is used. We show the exact path to do key recovery by explaining the detailed steps, using the PC oracle. In both scenarios, the new attack requires 53, 857 traces on average with much fewer PC oracle calls than the timing attack of Guo et al. CHES 2022 on an HQC implementation.
Cited by 12Open access
ZHAO Xin-jie, WANG Tao, ZHENG Yuan-yuan · SHILAP Revista de lepidopterología · 2010
Two access driven Cache timing analysis methods on both first four rounds and last four rounds of SMS4 encryption were proposed and discussed.On the precondition of not interfering SMS4 encryption,a spy process was designed to gather the un-accessed lookup table related Cache sets during first four rounds and last four rounds of SMS4 encryption,then transferred them into impossible lookup table indices,combing plaintext or cipher text to analyze the impossible key byte candidates,finally the initial SMS4 key was recovered.Experiment results demonstrate that multi-process sharing Cache space feature and SMS4 lookup table structure decide that SMS4 is vulnerable to Cache timing attack,for about 80 samples are enough to recover full 128bit SMS4 key during both first four rounds attack and last four rounds attack,so it’s necessary to take certain countermeasures to prevent this kind of attack.
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Helena Handschuh , et al. · 2007
This paper describes a known plaintext timing attack on the RC5 encryption algorithm. RC5 is a block cipher designed by Ron Rivest [1] in 1995. It has variable parameters such as the key size, the block length and the number of rounds. Our timing attack works against any version of RC5, but we will focus on the nominal version with 12 rounds, 64 bit blocks and a 128 bit key for simplicity. Timing attacks were invented by Paul Kocher in 1995 [2], and in his paper he mentions "RC5 is at risk on platforms where rotates run in non-constant time". We show how to exploit this property in order to recover the whole secret key in time complexity 2^28 in the best case and with 2^20 known plaintexts. We assume that we can make time measurements which enable us to deduce the total amount of rotations carried out during encryption of a known plaintext under an unknown key.
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Marjan Ghodrati · VTechWorks (Virginia Tech) · 2018
The extent of embedded systems' role in modern life has continuously increased over the years. Moreover, embedded systems are assuming highly critical functions with security requirements more than ever before. Electromagnetic fault injection (EMFI) is an efficient class of physical attacks that can compromise the immunity of secure cryptographic algorithms. Despite successful EMFI attacks, the effects of electromagnetic injection on a processor are not well understood. This includes lack of solid knowledge about how EMFI affects the circuit and deviates it from proper functionality. Also, effects of EM glitches on the global networks of a chip such as power, clock and reset network are not known. We believe to properly model EMFI and develop effective countermeasures, a deeper understanding of the EM effect on a chip is needed. In this thesis, we present a bottom-up analysis of EMFI effects on a RISC microprocessor. We study these effects at three levels: at the wire-level, at the chip-network level, and at the gate-level considering parameters such as EM-injection location and timing. We conclude that EMFI induces local timing errors implying current timing attack detection and prevention techniques can be adapted to overcome EMFI. To further validate our hypothesis, we integrate a configurable timing sensor into our microprocessor to evaluate its effectiveness against EMFI.
Cited by 2Open access
2016
t-Test Error detection into practice. To improve the feasibility of timing attack, the current study proposes an theoretical timing attack algorithms or have extended the existing ones. In 1998, Dhem et al. [8] employed timing attack into a Smartcard that stores an RSA private key. Schindler [19] proposed a timing attack against the implementation of RSA expo-nentiation which employs Chinese Remainder Theorem (CRT). Some papers [2,4] focused on putting the results of such the-oretical research into practice. OpenSSL is a well-known (open source) crypto library which is often used on Apache Web Servers to provide SSL functions. In 2003, Brumley and Boneh [4] demonstrated that timing attack can reveal RSA private
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Chloe Johansen Applegate, Alex Campbell · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 2021
GPS signals play essential roles in the electric subsector by providing precision timing used to synchronize and record measurements from a range of equipment. However, previous research has demonstrated that GPS signals can be spoofed or jammed relatively easily in order to interfere with timing-reliant equipment. This document outlines utility best practices for mitigating against timing attacks in the electric subsector based on an assessment of the difficulty and impact of realistic timing attacks and testing of the effectiveness of technologies capable of mitigating them. This analysis builds on research establishing the vulnerability of GPS-reliant timing equipment to jamming and spoofing by elaborating the difficulty, consequences, and mitigations for timing attacks that adversaries might realistically attempt. While timing attacks are relatively low-cost, low-sophistication, and capable of systemic consequences in the electric subsector, they can be effectively mitigated through well-targeted and diverse mitigations.
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Abd Ghafar, Amir Hamzah, Kamel Ariffin, Muhammad Rezal · Universiti Putra Malaysia Institutional Repository (Universiti Putra Malaysia) · 2014
Timing attack is an attack on the implementation of a cryptographic primitive. The attack collects leaked secret data via certain implementation techniques either on software or hardware. This paper provides an analysis of a theoretical timing attack on the AAβ algorithm. The attack dis- cussed in this paper gives avenues for secure implementation of AAβ against timing attacks. The simulation of the attack is important to provide invulnerability features for the algorithm in order to be implemented and embedded on applications. At the end of the attack, a method to overcome it will be introduced and it is called AAβ blinding.
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Werner Schindler · Lecture notes in computer science · 2002
Cited by 60Open access
Advait Kelapure, M. M. Chandane · 2015
Abstract—Timing Attacks are a type of side channel attacks. In timing attacks, leaking cache timing information is used as the side channel. If the information about cache timing of a software implementation of AES is collected and analyzed by an attacker, the secret key of a crypto system can be deduced. Hence AES is fallible to timing attack. There are a few countermeasures in the form of software code implementation which changes behavior of AES to manipulate its timing information. But it causes decrease in speed of computation which reduces the performance. So there is a need to implement a new more efficient countermeasure which this paper tries to suggest.
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Sinan Ameen Noman, Travis Atkison · Journal of The Colloquium for Information Systems Security Education · 2023
VANET is a type of Ad hoc network that enables the communication between vehicles and roadside units. It provides a broad range of applications, such as blind crossing, accident avoidance, protection, interactive route planning, traffic situation monitoring in real-time, etc. These applications are required to be very secure to achieve a reliable service and provide safety for drivers. This paper sheds light on three different types of attacks (Sybil Attack, Jamming Attack, Timing Attack) that can critically affect the vehicular ad hoc network environment. Furthermore, we present techniques that can overcome these attacks.
Cited by 4Open access
Yaseen H. Taha, Settana M. Abdulh, Naila A. Sadalla et al. · 2016
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