K. Slimani, J. Fragoso, Laurent Fesquet et al. · SPIRE - Sciences Po Institutional REpository · 2004
The power consumption of integrated circuits is one of the most problematic considerations affecting the design of high-performance chips and portable devices. The study of power-saving design methodologies now must also include subjects such as systems on chips, embedded software, and the future of microelectronics. Low-Power Electronics Design covers all major aspects of low-power design of ICs in deep submicron technologies and addresses emerging topics related to future design. This volume explores, in individual chapters written by expert authors, the many low-power techniques born during the past decade. It also discusses the many different domains and disciplines that impact power consumption, including processors, complex circuits, software, CAD tools, and energy sources and management. The authors delve into what many specialists predict about the future by presenting techniques that are promising but are not yet reality. They investigate nanotechnologies, optical circuits, ad hoc networks, e-textiles, as well as human powered sources of energy. Low-Power Electronics Design delivers a complete picture of today's methods for reducing power, and also illustrates the advances in chip design that may be commonplace 10 or 15 years from now.
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Robert L. Webb · 2010
The system clock has been omnipresent in most mainstream chip designs. While simplifying many design problems the clock has caused the problems of clock skew, high power consumption, electromagnetic interference, and worst-case performance. In recent years, as the timing constraints of synchronous designs have been squeezed ever tighter, the efficiencies of asynchronous designs have become more attractive. By removing the clock, these issues can be mitigated. How- ever, asynchronous designs are generally more complex and difficult to debug. In this paper I discuss the advantages of asynchronous processors and the specifics of some asynchronous designs, outline the roadblocks to asynchronous processor design, and propose a series of asynchronous designs to be used by students in tandem with traditional synchronous designs when taking an undergraduate computer architecture course.
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Michael A. Bender, Cynthia A. Phillips · 2007
This paper addresses the problem of scheduling a DAG of unit-length tasks on asynchronous processors, that is, processors having different and changing speeds. The objective is to minimize the makespan, that is, the time to execute the entire DAG. Asynchrony is modeled by an oblivious adversary, which is assumed to determine the processor speeds at each point in time. The oblivious adversary may change processor speeds arbitrarily and arbitrarily often, but makes speed decisions independently of any random choices of the scheduling algorithm.
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Benoı̂t Caillaud, Paul Caspi, Alain Girault et al. · HAL (Le Centre pour la Communication Scientifique Directe) · 1997
: This paper addresses the problem of distributed program synthesis. In the first part, we formalize the distribution process and prove its correctness, i.e. that the initial centralized program's behavior is equivalent to the corresponding distributed's one. In order to achieve that, we first represent the program by a finite transition system, labeled by the program's actions. Then we derive an independence relation over the actions from the control and data dependencies. This leads to represent the program by an order-automaton, whose transitions are labeled partial orders coding for an action and its dependencies with other actions. In the second part, we show how such an order-automaton can be practically used to derive a distributed program. Key-words: theory of parallel and distributed computation, automata and formal languages (R'esum'e : tsvp) This work has been partially supported by PRC C 3 (CNRS), GRECO Automatique action C2A and Minist`ere de l'Enseignement Sup'erieur e...
Cited by 20Open access
M.R. Karthikeyan, S.K. Nandy · 1997
Summary form only given. We propose an asynchronous architecture for digital signal processors. This is based on a modification of the counterflow pipeline. In addition to registers, we apply the counterflow technique to memory operands as well. This results in an asynchronous architecture with good performance potential for DSP. We describe the architecture below.
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Nancy Lynch · SMARTech Repository (Georgia Institute of Technology) · 1980
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Gennette Gill, Montek Singh · 2008
Changes in modern semiconductor technology are making computation so inexpensive that individual chips will soon contain thousands of processing units (PUs). Asynchronous design techniques can make multiprocessor chips more efficient by allowing idle processors
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Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson et al. · IEEE Journal of Solid-State Circuits · 2008
An array of simple programmable processors is implemented in 0.18 mum CMOS and contains 36 asynchronously clocked independent processors. Each processor occupies 0.66 and is fully functional at a clock rate of 520-540 MHz at 1.8 V and over 600 MHz at 2.0 V. Processors dissipate an average of 32 mW under typical conditions at 1.8 V and 475 MHz, and 2.4 mW at 0.9 V and 116 MHz while executing applications such as a JPEG encoder core and a fully compliant IEEE 802.11 a/g wireless LAN baseband transmitter.
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Karthikeyan Nandy Texas, M R Karthikeyan, S K Nandy · 1997
We propose an asynchronous#1# architecture for digi# tal signal processors. This is basedonamodi#cation of the counter#ow pipeline#2#. In addition to regis# ters# we apply the counter#ow technique to memory operands as well. This results in an asynchronous ar# chitecture with goodperformancepotential for DSP. We describe the architecturebelow. 1 Counter#ow We propose a modi#cation to the counter#ow pipeline #2## which has several interesting properties useful for DSP. Operations in our pipeline can have memory or register operands and targets. We associate each memory operand or result with a hash code. These codes# distinguished from register codes by a special pre#x# are placed in the operand or result ID #elds as the register codes are. This extension is useful for DSP algorithms where computations depend on im# mediately preceding computations and operands usu# ally are from memory. 2 The Architecture The architecture we propose will have the following parts# A fetch# pre#deco...
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Caspi, Paul, Caillaud, Benoit, Jard, Claude et al. · OpenGrey (Institut de l'Information Scientifique et Technique) · 1994
Programme 1 et 2 - Architectures paralleles, bases de donnees, reseaux et systemes distribues - Calcul symbolique, programmation et genie logiciel. Projets Pampa et Spectre
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Ran Ginosar, N. Michell · ACM SIGARCH Computer Architecture News · 1990
An asynchronous version of the pipelined R3000 and DLX processors, the A3000, is being designed. Simulation was employed to investigate the potential speed-up obtainable due to the asynchronous operation. Preliminary results show up to a 64% improvement in performance.
Cited by 7Open access
B. Galilee, Franck Mamalet, Marc Renaudin et al. · 2003
A joint algorithm-architecture analysis leads to a new version of picture segmentation system adapted to multimedia mobile terminal constraints. The asynchronous processors network, with a granularity level of one processor per pixel, based on data flow model, takes less than 10 /spl mu/s to segment a SQCIF $88*72 pixels - image (about 2000 times faster than the classical sequential watershed algorithms). The main originality of the proposed algorithm is only one global synchronization point is needed in order to complete the segmentation transformation, instead of the three (or more) classical points: minima detection, labelization and flooding. Our system tends to cope with multimedia mobile phones constraints, i.e. real time computing circuit, low power. We have simulated and validated this system thanks to "SystemC" library; VHDL synchronous prototyping shows up results accordingly.
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Rachit Saini · 2018
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Di Blas, Andrea, Turin Politecnico (Italy). Dipartimento di Elettronica · OpenGrey (Institut de l'Information Scientifique et Technique) · 1999
Dottorato di ricerca in ingegneria elettronica e delle comunicazioni. 11. ciclo. Tutore Pierluigi Civera. Coordinatore Ivo Montrosset
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R. H. Barlow, D. J. Evans, J. Shanehchi · Computer Physics Communications · 1982
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Yangdong Deng, Yuhao Zhu, Wang Bo · Lecture notes in earth system sciences · 2013
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Jeremy Sugerman, Tim Foley, Shigeatsu Yoshioka et al. · 2006
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Albin Göransson · KTH Publication Database DiVA (KTH Royal Institute of Technology) · 2018
We solve initial boundary value problems with information unavailable at random time-steps. The randomly unavailable information represents asynchrony between processing elements. To approximate the initial boundary value problem, finite difference operators with summation-by-parts proper-ties and weak boundary procedures are used. Utilizing the energy method, we derive energy estimates for synchronous and asynchronous problems. The simulations show that the solutions may remain accurate and stable, even in the asynchronous case.
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Arvind And Rebello, D. K. Arvind, V. E. F. Rebello · 1996
This paper investigates issues which impinge on the design of static instruction schedulers for micronetbased asynchronous processor (MAP) architectures. The micronet model exposes both temporal and spatial concurrency within a processor. A list scheduling algorithm is described which has been optimised with MAP-specific heuristics. Their performance on some program graphs are presented and conclusions are drawn on the suitability of MAP as targets for ILP compilers.
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2007
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