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About 1,746 papers for “double error correction”

Efficiency Estimation of Single Error Correction, Double Error Detection and Double-Adjacent-Error Correction Codes

Nikita Kustov, E. S. Lepeshkina, В Х Ханов · Advances in intelligent systems and computing · 2020

Cited by 2

Double Entry Bookkeeping and Error Correction

Anil Arya, John Fellingham, Doug Schroeder et al. · RePEc: Research Papers in Economics

We formally establish the link between linear algebra and the double entry bookkeeping system: the system transforms a vector of numerical values corresponding to transaction amounts to a financial statements vector through matrix multiplication. The matrix is called a generator matrix (it is used to generate financial statements). This representation of double entry bookkeeping allows us to simultaneously apply coding theory and linear algebra's nullspace to the analysis of the relationship between transactions and account balances. We show how to construct a parity check matrix directly from the generator matrix. Our main results demonstrate how the parity check matrix can be used to detect and correct errors which can not be corrected and may not even be detected by the usual trial balance check. (The trial balance check would be a subset of possible checks performed via the parity check matrix.) The idea is that there are more restrictions on the relations among the transaction which are captured by the generator matrix. These restrictions are then exploited by the parity check matrix, allowing for detection and correction of errors.

Cited by 0

Multiresidue codes for double error correction

Paulo P. Monteiro, T.R.N. Rao · 1972

A new class of (separate) multiresidue codes has been proposed, which is capable of double error correction. The codes are derived from a class of AN codes where A is of the form π i=1 3 (2 ki -1). Previously all discussions on separate code implementation had restricted themselves to single error correcting codes only. We have shown that these multiple-error correcting separate codes can be relatively easily implemented as the check bases are of the form 2 k -1. A comparison with the multiresidue codes derived from Barrows-Mandelbaum codes has shown that these codes have in general a higher information rate and an easier implementation.

Cited by 1

A single error correction double burst error detection code

L. Bodnar, G. Chapelle · 2004

Particle radiation induced single event upset (SEU), if undetected in computer memory, can have potentially catastrophic effects. An improved error indicating system capable of correcting single errors and detecting multiple adjacent bit burst errors is discussed. This system uses the minimum number of redundant bits possible, and in some cases the number of bits is equivalent to simple parity checking.

Cited by 3

An Improved (24, 16) OLS Code for Single Error Correction-Double Adjacent Error Correction-Triple Adjacent Error Correction

Sayan Tripathi, Jhilam Jana, Jaydeb Bhaumik · Lecture notes in networks and systems · 2023

Cited by 3

Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes

Shanshan Liu, Pedro Reviriego, Juan Antonio Maestro et al. · Microelectronics Reliability · 2018

Cited by 10

Double-burst-error correction with cyclic codes.

Jang, Kenneth Kin Yok · eScholarship@McGill (McGill) · 1972

There have been many developments in the area of burst detection and correction during the pa st de cade , with emphasis mostly on cyClic codes due to their ease of implementation and transmission.Different concepts in the design of burst-.error correction codes have been tried.In particular cyclic produt codes have been known to be attractiv~ for burst-error correction.These codes are made up of a number of subcodc;!s which are themselves cyclic codes, and an error pattern goes undetected if and only if the subsyndromes (of the subcodes) are individually zew.Decoding consists of extracting informatic;m from theerror patterns obtained in each of the subsyndromes.Furthermore, the correctable burst length does not depend on the minimum weight of the code, but only on the subsyndrome lengths.A specific class of cyclic product codes (and a generalization of Gilbert codes) is found to be efficient in mu Itiple ':'burst-error detection.Sorne theorems on the single and double burst-error correction capabilities of these codes will be given and a decoding procedure wH 1 be shown for two bursts.General izati.on to multiple -burstcorrection methods will be considered.

Cited by 0Open access

Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection

Luis-J. Saiz-Adalid, Joaquín Gracia-Morán, Daniel Gil-Tomás et al. · IEEE Access · 2019

Reliable computer systems employ error control codes (ECCs) to protect information from errors. For example, memories are frequently protected using single error correction-double error detection (SEC-DED) codes. ECCs are traditionally designed to minimize the number of redundant bits, as they are added to each word in the whole memory. Nevertheless, using an ECC introduces encoding and decoding latencies, silicon area usage and power consumption. In other computer units, these parameters should be optimized, and redundancy would be less important. For example, protecting registers against errors remains a major concern for deep sub-micron systems due to technology scaling. In this case, an important requirement for register protection is to keep encoding and decoding latencies as short as possible. Ultrafast error control codes achieve very low delays, independently of the word length, increasing the redundancy. This paper summarizes previous works on Ultrafast codes (SEC and SEC-DED), and proposes new codes combining double error detection and adjacent error correction. We have implemented, synthesized and compared different Ultrafast codes with other state-of-the-art fast codes. The results show the validity of the approach, achieving low latencies and a good balance with silicon area and power consumption.

Cited by 14Open access

RANDOM-DOUBLE-TRACK-ERROR CORRECTION IN MAGNETIC TAPES.

Ashutosh Kumar Bhatt, Larry L. Kinney · 1980

Cited by 0

A Double Error-Correction Scheme for Peripheral Systems

V. Malhotra, R. Fisher · IEEE Transactions on Computers · 1976

In multiple digital recording peripheral systems, the errors which are encountered are burst-type errors which may occur in several tracks or channels. This paper discusses methods and implementation procedures for correcting a series of errors or erasures of arbitrary length in any one or two tracks of a multi-channel system. We have shown that such errors in multiple tracks may be detected and corrected using a two-redundant Hamming code over a Galois field mathematical structure in conjunction with error track pointers. The detection/correction scheme considered here can correct N-bit blocks, thereby correcting an error burst of arbitrary length in any single or pair of tracks. The error-correction (EC) scheme is shown to be applicable to two types of data formats or arrays. Additional error detection is provided to check the validity of error correction to enhance reliability above that of double error correction. Implementation methods pertaining to the above EC scheme are discussed. Examples of single and double error corrections for two types of data formats or arrays are included.

Cited by 1

Efficient error detection in Double Error Correction BCH codes for memory applications

Pedro Reviriego, Costas Argyrides, Juan Antonio Maestro · Microelectronics Reliability · 2012

Cited by 27

Reducing the Cost of Triple Adjacent Error Correction in Double Error Correction Orthogonal Latin Square Codes

Shanshan Liu, Pedro Reviriego, Liyi Xiao et al. · IEEE Transactions on Device and Materials Reliability · 2016

As multiple cell upsets (MCUs) become more frequent on SRAM memory devices, there is a growing interest on error correction codes that can correct multibit errors. Orthogonal Latin square (OLS) codes are an interesting option due to their low-complexity decoding and modular construction. Several works have also shown that it is possible to improve OLS codes, for example, by providing additional error correction for adjacent errors. In particular, a method has been recently proposed to implement triple adjacent error correction (TAEC) on double error correction (DEC) OLS codes. That scheme exploits the properties of OLS codes to achieve TAEC using an independent error correction logic and does not require additional parity check bits. This can be useful as, in many cases, the errors caused by MCUs are adjacent. In this paper, a more efficient technique to implement TAEC for DEC OLS codes is presented. The proposed method can be used as long as there are sufficient parity check bits to interleave among the data bits. This is the case for DEC OLS codes of up to 64 bits, which can be used to protect 16- and 64-bit data words. The new scheme uses an optimized bit placement that interleaves data and parity check bits to simplify the decoding. In particular, correction of single, double, and triple adjacent errors is now achieved with a single circuit that is a minor modification of the standard OLS decoding. This reduces area, power, and delay, making the new scheme attractive for circuit implementations.

Cited by 10

Double Bits Error Correction for Computational Grid with CRC

Nima Jafari Navimipour, Seyed Hasan Es-hagi · International Journal of Computer and Electrical Engineering · 2009

In grid system error during sending information due to devastating factors like external electromagnetic sources and noise is inevitable. The Cyclic Redundancy Check (CRC) method is used for error detection. CRC is used to control such factors in received information. In this paper, the new method based on CRC has been introduced that is able to detect the exact place of double bits error and correct them. In this method the receiver divide the received data on polynomial generator, g(x), and then get the remainder. Receiver can correct double bits error by comparing the remainder and the content of the look-up table. The result show that presented method can reduce the traffic for application that have low bit error rate (BER).

Cited by 0Open access

On the Positional Single Error Correction and Double Error Detection in Racetrack Memories

Awais Saeed, Ubaid U. Fayyaz, Ahsan Tahir et al. · IEEE Access · 2023

In the era of non-volatile memories, the racetrack memory is a promising technology to pack hundreds of bits in a magnetic nanowire. A solid-state read head is grown alongside the nanowire to sense individual bits which are pushed across the head by a shifting force. However, the probabilistic nature of this shifting movement inflicts positional errors. Therefore, robust and low-cost error correcting codes are essential for a reliable alternative in on-chip memories and storage applications. Recent works focus on Varshamov-Tenengolts (VT) codes which can correct all single bit insertions and deletions. However, VT codes are incapable of detecting multiple deletions/insertions. Because a positional error corrupts multiple data words, multi-bit positional error detection is critical for racetrack memories. In this article, we propose a novel positional single error correction and double error detection (P-SECDED) code in the context of racetrack memories with a single read head. In particular, we adopt a postamble-based approach where a VT-encoded codeword appends a carefully selected bit-pattern, stored on the racetrack. We rigorously analyze the limitations of the postamble method, and deduce a criterion for postamble selection. We further provide a methodology to optimize this postamble selection in order to correct all single-bit errors and as much of two-bit errors as possible. Finally, we prove that all incurable two-bit errors are successfully detected. To the best of our knowledge, this work is the first attempt to provide P-SECDED fault-tolerance to three-dimensional racetrack memories which cannot afford multiple read heads.

Cited by 3Open access

Double Adjacent Error Correction Codes for Ultra-Fast Cache Memories

Rabah Abood Ahmed, Khairulmizam Samsuldin · IEEE Access · 2024

Error correction codes are commonly used to protect cache memories from soft errors. As technology feature size scales deeper into sub-nanometer regime, radiation-induced soft error can causes double adjacent error (DAE). Several double adjacent error correction (DAEC) codes have been introduced to address DAEs, however, they miscorrect some nonadjacent double errors. In progress, a class of DAEC orthogonal Latin squares (OLS) codes is introduced to eliminates all miscorrections, using the orthogonality property of OLS codes, and also reduces the decoding delay time. The main drawback comes from the large number of check bits, imposed by the conventional OLS codes. In this paper, two coding approaches are developed based on a modified SEC OLS coding scheme that requires less number of check bits. The first approach is a class of SEC-DED-DAEC codes proposed to reduce the number of check bits compared to the existing SEC-DED-DAEC OLS codes. The second approach is a class of SEC-DAEC codes with a very high speed decoding process. This approach is designed as SEC OLS scheme and integrated with new modules for detecting and correcting the DAE error. The evaluation of the proposed SEC-DAEC codes in 45nm ASIC technology shows promising results. The decoding delay for protecting 16, 64, and 256 bit data words is less by at least 20% over existing SEC-DED and SEC-DAEC codes.

Cited by 2Open access