Skip to content
Free planNo credit card requiredStart writing
AI for Research home
AI for Research home
Dashboard
Sign inGet started

Search 250 million research papers

Read the abstract, see who wrote it and who cites it, and get the citation in APA, MLA, Chicago or Harvard.

About 9,748 papers for “dynamic CMOS”

Asynchronous design in dynamic CMOS

Juhie Ahmed, S.G. Zaky · 2002

The design for dynamic CMOS cells that can be used as building blocks in an asynchronous pipeline are discussed in this paper. The proposed circuit elements are variations on TSPC logic using Sutherland's micropipeline structure combined with dual rail logic to detect operation completion. The resulting cell occupies more area than a TSPC cell, but has higher functionality because of the built-in data flow control mechanisms provided by the handshake signaling of the micropipeline structure.

Cited by 0

High dynamic range cmos filter

M.S. Qureshi, P.E. Allen · 2005

Summary form only given. Implementation of high dynamic range on-chip 70 MHz gm-C (transconductor-capacitor) filter for a UMTS (WCDMA) superheterodyne receiver is described. The filter is designed in National Semiconductor's 0.18 micron standard CMOS process. Chebyshev approximation is used to implement a 6th order filter in active gm-C. Positive feedback is used to realize a large quality factor (Q). This filter provides blocker attenuation with dynamic range (DR) of 42 dB and with power consumption of 21.78 mW.

Cited by 0

CMOS ternary dynamic differential logic

A. Herrfeld, Siegbert Hentschke · Electronics Letters · 1994

A new ternary dynamic differential logic (TDDL) has been developed with some favourable properties: high noise margin, standard CMOS process technology restricted to enhancement p- and n-MOSFETs, and no static power consumption. The complete TDDL circuit for a radix 3 full adder is presented.

Cited by 12

PWM CMOS Imager ????????? ????????? ??? ??????, ??? ?????? Dynamic Pixel ?????? ??????

????????? · The Royal Society of Chemistry’s Journals, Books and Databases (The Royal Society of Chemistry) · 2010

A typical CMOS image sensor (CIS) amplifiers voltage or current through source follow to read the value of the pixel. However, the source-follower used in a CMOS active pixel sensor (APS) suffers from degraded SNR due to its gain being less than unity. In this paper Pulse Width Modulation (PWM) of the structure of a common-gate-amplifier has proposed a new pixel structure. A PWM pixel can convert light intensity to a digital pulse width by using an in-pixel comparator with a low power-supply voltage without any degradation of signal-to-noise ratio (SNR). To reduce the size of these pixels, with a comparison of the transistor through the commongate-amplifier structure to a 4-transistor pixel structure was proposed. proposed pixel has Larger signal range, low voltage leakage current and low power consumption than the conventional structure of the pixel.

Cited by 0

High dynamic range CMOS-integrated biosensors

Ritu Raj Singh · Texas ScholarWorks (Texas Digital Library) · 2013

Biosensors are extremely powerful analytical tools instrumental for detection and quantification of bio-molecules such as DNA, peptides and even metabolites. The recent decade has seen a surge in biosensing applications ranging from molecular diagnostics, environmental monitoring, basic life science research, forensics and biothreat monitoring. The existing biosensor systems of today, however, have several limitations. They are expensive, bulky in size, power hungry, hard to use and with access limited to core facilities. Among other disadvantages, these impediments discourage the availability of point-of-care testing and low cost in-vitro diagnostics (IVD) in locations such as developing and third world countries. The main bottleneck in the development of low-cost and compact biosensors is the effective and efficient integration of several complex components present inside a typical biosensor. These components are the sample preparation, biomolecular recognition, signal transduction and data analysis. With vii the recent advancements in very large scale integration (VLSI) and fabrication technologies, it is now possible to integrate several of these biosensing components into a small form factor. This thesis proposes leveraging the utilization of VLSI technology to develop a low-cost, miniature, portable, fast analysis, high throughput and low power consumption biosensor solution. Apart from the miniaturization bene- fits, employing VLSI technology facilitates low-cost, high yield and low process variation. We present complementary metal-oxide semiconductor (CMOS) integrated microsystem solutions for fluorescence, bioluminescence and electrochemical biosensing. Simulation models are provided for the microsystems and the specifications for the constituent components derived. A common problem in the transducer development of biosensors that we specifically focus on, is the presence of a large non-informative signal called the background signal. This background signal can be several orders of magnitudes higher than the signal of interest and it reduces the overall sensitivity of the biosensor. Existing transducer solutions rely on very high dynamic range, expensive and power hungry solutions to solve the problem of high background signal. To address the problem of overwhelming background signal, this thesis proposes an active background subtraction architecture merged with a Σ∆ modulator. The robust, versatile architecture can be conveniently employed for optical and electrochemical sensing. The proposed architecture attenuates the background signal very early in the signal chain, achieving high dyviii namic range while significantly relaxing the performance requirements of the subsequent circuit blocks in terms of power dissipation, area and bandwidth requirements. To validate the proposed solution, two CMOS IC prototypes were developed for optical and electrochemical sensing respectively. A 12 × 12 array of Σ∆ photodetector with in-pixel background subtraction was developed in 0.18µm standard CMOS technology. The pixel performance has been validated with over 140dB dynamic range and the ability of subtract the background subtraction current validated from 10nA to 10fA. Real time pyrosequencing experiment has also been performed utilizing the photodetector array. A 12 × 12 array of Σ∆ electrochemical sensor with in-pixel background subtraction was developed in 0.18µm standard CMOS technology. Capacitive charge redistribution circuit architecture for bipolar current measurements was employed. The circuit performance was validated over the wide input current range of 100nA to 1pA.

Cited by 0Open access

Noise in Digital Dynamic CMOS Circuits

2009

Dynamic logic is an attractive circuit technique giving reduced area and increased speed for CMOS circuits. Static logic has a major advantage: its superior noise margins. To be able to choose between a static and a dynamic implementation of a design, we need to know the requirements for dynamic logic. Here we try to identify possible errors, estimate the limits and discuss some possible soIutioDS when considering noise in dynamic drcuits.

Cited by 2

TESTING BiCMOS AND DYNAMIC CMOS LOGIC

Siyad Chih-hua Ma, Siyad Chih-hua Ma, Siyad Chih-hua Ma · 1995

: This technical report contains the text of Siyad Ma's thesis "Testing BiCMOS and Dynamic CMOS Logic." Funding: This research was supported in part by the Innovative Science and Technology Office of the Strategic Defense Initiative Organization and administered through the Office of Naval Research under Contract No. N00014-92-J-1782, and by the National Science Foundation under Grant No. MIP-9107760. TESTING BiCMOS AND DYNAMIC CMOS LOGIC Siyad Chih-Hua Ma CRC Technical Report No. 95-1 (CSL TR 95-669) June 1995 CENTER FOR RELIABLE COMPUTING Computer Systems Laboratory Departments of Electrical Engineering and Computer Science Stanford University Stanford, CA 94305-4055 Copyright 1995 Siyad C. Ma All Rights Reserved TESTING BiCMOS AND DYNAMIC CMOS LOGIC A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND THE COMMITTEE ON GRADUATE STUDIES OF STANFORD UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSO...

Cited by 0

An Review of Dynamic CMOS Comparators

Yuchuan Liu · Highlights in Science Engineering and Technology · 2023

CMOS dynamic comparators contributes a major role on the implementation of mixed signal successive approximation register (SAR) type of analog to digital converters (ADC). High precision, dynamic range, low voltage operation, high speed, low power consumption, reliability and offset voltage are the critical factors to be considered while designing CMOS dynamic comparators. This paper reviewed the performance of some popular dynamic CMOS comparators such as StrongARM latch comparator, double- tail dynamic-latched comparator, dynamic bias comparator and triple stage somparator.

Cited by 0Open access

Dynamic range expansion in CMOS imaging

Schrey, Olaf · DuEPublico (University of Duisburg-Essen) · 2006

Nearly 80% of the worldwide semiconductor market volume is covered by standard-CMOS-technology products. Due to the increasing demand on highly flexible, reliable and robust image sensors from many different industry parts, CMOS-technology has become more and more attractive, since it offers several features in contrast to the CCD-technology. The focus of this work lies on the development of high dynamic range CMOS image sensors suitable for industrial, automotive and consumer applications. The developed sensors should yield more powerful and cost-saving system solutions compared with CCD-sensor systems that are available from the market. The work concentrates on mainly linear CMOS-sensors offering a linear dependency between illumination and electronic signal representation. The developed sensors achieve a dynamic range of more than 90dB, which is much more than CCD´s have with 50-60dB. Two sensors are presented with the first one using a mixed logarithmic/linear characteristic and the second sensor working with a multi-illumination scheme using different exposure/integration times, resp. The work finishes with a discussion of the presented sensors and their underlying signal processing algorithms and a short outlook on future developments.

Cited by 0

Design of CMOS dynamic reference ADC

Lee, Ler Yang · DR-NTU (Nanyang Technological University) · 2015

A low power 8-bit dynamic reference ADC is presented. This ADC is designed based on the Charter 0.18μm technology and the circuit is designed in Cadence Virtuoso schematic editor and simulated in Virtuoso Analog Design Environment. MATLAB is also needed for data analysis. The dynamic reference ADC is asynchronous and comprises of comparator, R-2R resistive network and voltage reference. It employs binary search algorithm to significantly reduce the number of comparators needed and hence only 8 comparators are needed for 8-bit ADC. The comparator is high speed and has a hysteresis window of 1mV. The voltage reference uses the current mode approach bandgap circuit and has a temperature coefficient of 15.2ppm/K. The dynamic reference is generated by a built-in current steering DAC which consists of the voltage reference and the R-2R resistive network. The dynamic reference ADC is designed to operate under 1V power supply and have an input range of 0-600mV. It achieves a 41.875dB signal-to-noise-plus-distortion (SNDR) and ENOB of 6.43 bits with a sampling rate of 200kHz.

Cited by 0

CMOS Transconductor With Increased Dynamic Range

Prodanov, Vladimir I. · DigitalCommons - CalPoly (California State Polytechnic University) · 2003

A CMOS transconductor that operates with increased dynamic range while maintaining one or more other basic operating characteristics at substantially the same value in comparison to a prior art transconductor circuit is provided. One embodiment, among others, comprises an input stage circuit comprising several pluralities of transistors with each plurality configured such that certain terminals of the transistors are electrically connected, and the several pluralities are electrically interconnected through one or more terminals of each plurality. Another embodiment comprises modifying an input stage of an existing transconductor circuit to provide a transconductor circuit that operates with increased dynamic range while maintaining one or more other basic operating characteristics at substantially the same value in comparison to the existing transconductor circuit.

Cited by 0Open access

Noise in digital dynamic CMOS circuits

P. Larsson, C. Svensson · IEEE Journal of Solid-State Circuits · 1994

Dynamic logic is an attractive circuit technique giving reduced area and increased speed for CMOS circuits. Static logic has a major advantage: its superior noise margins. To be able to choose between a static and a dynamic implementation of a design, we need to know the requirements for dynamic logic. Here we try to identify possible errors, estimate the limits and discuss some possible solutions when considering noise in dynamic circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 133

Design of CMOS Dynamic Circuits with . . .

Fernando Mendoza-Hernandez, O Mendoza-hernández, Monico Linares et al. · 2007

this paper we present a new noise-tolerant dynamic circuit technique suitable for pipelined dynamic digital circuits. The effectiveness of this technique is demonstrated by means of HSPICE simulations for two kind of gates, CMOS AND and OR gates, both TSPC and Domino. In order to have a clear idea about this proposal&amp;apos;s noise immunity improvement we compare its performance with previous works. Simulation results show that the proposed technique has an improvement in the noise tolerance and the \t 9999 quotient over the conventional dynamic logic and the previous noise-tolerant dynamic circuit techniques with a slight delay and power increase

Cited by 0

Wide dynamic range CMOS image sensor

Das, Dipayan · OpenGrey (Institut de l'Information Scientifique et Technique) · 2011

• Abstract Integrated digital imaging systems are widely used in consumer electronics today. Current digital image sensors have a linear respeiiSt. The limited dynamic range of linear digital image sensors results in saturation when the input dynamic range of the scene is larger than that of the camera. This limitation could be overcome using pixels with an output that is proportional to the logarithm of the detected photocurrent. Conventional CMOS pixels with a logarithmic response, using a transistor operating in the sub-threshold region, are capable of capturing wide dynamic range scenes with more than six decades of illumination intensity. But these pixels suffer from fixed pattern noise, slow response and low sensitivity. A five transistor (5T) pixel circuit for a standard 0.35-fLm CMOS process which integrates the photocurrent linearly and capable of a logarithmic response is described in the thesis. A key component of the 5T pixel is a time-dependent reference voltage. This voltage is applied to the gate of one of the transistors inside each pixel in the array for the duration of the exposure to generate a logarithmic response. A model derived to generate the reference voltage is described. Improvements were made to the reference voltage model to take into consideration the non-ideal effects such as charge feedthrough and threshold voltage variations. A potential problem associated with successfully tonemapping low photo currents with the 5T pixel has been described and a method to calculate the optimal value of reference current Iret proposed. This was shown to lead to an optimum photoresponse. Measurement results from fabricated 1-D and 2-D arrays of 5T pixels are presented and analysed. An overall DR of 97-dB (almost 5 decades) has been achieved from 100 mlux to 6.7 Klux. The slope of the logarithmic photoresponse was shown to be adjustable and controlled by the slope parameter S in the reference voltage model. A large output swing of over 1 V due to the large photoresponse slope in the logarithmic region results in greater signal-to-noise ratio compared to the conventional logarithmic pixel based on the subthreshold transistor operation (60 m V/decade). Digital and analogue reference voltage generating techniques are described with circuits implemented in 0.35-fLm CM OS process. Finally, a 5T NMOS pixel that is capable of WDR imaging with superior low-light performance (23 mlux) and greater DR (1l0-dB) than the 5T PMOS pixel is described. [ a

Cited by 0Open access

Dynamic Power Saving for CMOS Circuits

Kim Ho Yeap, Len Luet Ng, Ahmad Uzair Mazlan et al. · Jurnal Kejuruteraan · 2024

With more functionalities being integrated into a microchip today, higher processing power is drawn. As a result of this, clock and logic power consumption has turned out to be a critical issue to be coped with by chip designers. In this paper, we present various power-saving approaches employed in complementary metal oxide semiconductor (CMOS) circuit designs. The approaches involve restructuring the logic circuits, performing clock gating, and selecting the appropriate circuits for counters and frequency divisions. In order to show their efficacies in power optimization, the approaches were applied to a phase-locked loop (PLL), clock divider (CD), full adder (FA), counter, arithmetic logic unit (ALU), and microprocessor without interlocked pipelined stages (MIPS) circuits and validated using Intel Quartus Prime Lite and Mentor Graphics Modelsim. The following conclusions can be drawn from the results: Firstly, the efficacy of minimizing power dissipation using logic restructuring is found to be in direct proportion with the rate of the switching activity (SA); secondly, a maximum of 3.5% of thermal power dissipation can be saved using clock gating; thirdly, gray counters give the lowest power consumption; and, finally, the thermal power estimation for the phase-locked loop (PLL) is relatively higher than that for the clock divider (CD) when both of them are implemented for dividing frequencies.

Cited by 0Open access