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Fault Simulation

The MIT Press eBooks · 1985

Cited by 3

Fault Simulation

2021

Simulation has been used for modelling rotors, in particular those operating in a speed range covering a number of critical speeds, and with fluid film bearings, with nonlinear and time varying properties depending on factors such as speed, load, and lubricant viscosity. This chapter illustrates the advantages of fault simulation, using examples of gears, rolling element bearings, geared systems, and internal combustion engines. Before the faults can be simulated, there must be a simulation model of the gearbox in healthy condition, into which the faults can be introduced. An idea of the required complexity of lumped parameter models (LPMs) can be gained by considering the way in which the various inertias and stiffness elements interact as the speed of a geared system is increased. Since extended rough faults had been shown to give very different symptoms from local faults, a rough fault was simulated in the bearing model and inserted into the 34 DOF LPM.

Cited by 0

Speeding up Fault Simulation using Parallel Fault Simulation

Jiahua Fan, Zhifeng Zhang · Procedia Engineering · 2011

In this paper, a novel approach is introduced on accelerating the fault simulation speed on field programmable gate array (FPGA). The approach is based on parallel simulation methodology. More than one faulty circuit is handled in the fault simulation system, but the relative area overhead is low and it will accelerate the simulation process. A new metrics – Speedup relative to the Ratio of Hardware Overhead (SRHO) is introduced, by which the experimental results are evaluated. Experimental results in terms of simulation time, hardware overhead and SRHO for ISCAS-85 benchmark circuits are compared to a previous work to show its advantage.

Cited by 2Open access

Transition Fault Simulation

J.A. Waicukauski, Eric Lindbloom, Barry K. Rosen et al. · IEEE Design & Test of Computers · 1987

Delay fault testing is becoming more important as VLSI chips become more complex. Components that are fragments of functions, such as those in gate-array designs, need a general model of a delay fault and a feasible method of generating test patterns and simulating the fault. The authors present such a model, called a transition fault, which when used with parallel-pattern, single-fault propagation, is an efficient way to simulate delay faults. The authors describe results from 10 benchmark designs and discuss add-ons to a stuck fault simulator to enable transition fault simulation. Their experiments show that delay fault simulation can be done of random patterns in less than 10% more time than needed for a stuck fault simulation.

Cited by 401

Fault Injection Simulation:

Variance Reduction Technique, Aad P. A. Van Moorsel, Boudewijn R. Haverkort et al. · 1991

Cited by 0

Fault Simulation Algorithms

Sobhit Saxena · 2020

This chapter describes basics of simulation and its categorization into logic and fault simulation. The importance of fault simulation algorithms before actual testing on hardware is explained. Evolution of algorithms for reducing test time from simplest serial to differential fault simulation algorithm is described by explaining each algorithm. Identification of test vectors by fault simulation makes it different from logic simulation in which all possible inputs are applied for functionality verification. The concept of fault simulation is further practically implemented using Verilog language in which parallel and concurrent algorithms are implemented and simulation results in terms of waveforms are explained for better understanding.

Cited by 0

Statistical Fault Simulation

Jins Davis Alexander · 2008

Fault simulation is used for the development or evaluation of manufacturing tests. However with the increase in the number of gates in the circuit, the number of faults increases proportionally resulting in high computational time for a complete fault simulation. The complexity is found to increase at least as the square of the number of gates and thus is exponential in nature. To overcome the high computational requirements, statistical sampling methods have been proposed. In fault sampling, a subset of the total faults known as fault sample is used for simulation. The fault coverage obtained in this simulation is then used to estimate the fault coverage of the complete

Cited by 0

Fault Sampling and Statistical Fault Simulation

2008

Abstract—Techniques and theories regarding statistical fault simulation are presented. The literature regarding statistical fault simulation is explored from its beginning ideas to presentday applications. Results from different algorithms and applications found in the literature are given. As an example of fault sampling, the affects of fault sampling for fault coverage estimation is shown on the s35932 benchmark circuit. For this example, as the sample size increases, the error decreases until the estimated coverage approaches the true fault coverage. A

Cited by 0

VECTOR-LOGIC FAULT SIMULATION

Vladimir Hahanov, Svetlana Chumachenko, E. I. Lytvynova et al. · Radio Electronics Computer Science Control · 2024

Context. The technological trends of Design&Test computing for the IT industry and academic science are determined by the following directions: in-memory computing, immersive computing, AI computing, focused on energy saving and reduction of computing time when providing services. A mechanism for simulating faults as addresses on smart data structures is proposed, which eliminates the algorithm for simulating input test sets to obtain a test map for logic functionality. The proposed mechanism is focused on the service of SoC IP-cores under the control of the IEEE 1500 standard, which can be perceived positively by engineers in the EDA market. Objective. The purpose of the research is time- and energy-saving mechanisms for simulating malfunctions, such as addresses, by using read-write transactions of in-memory computing to build a test map of any functionality on smart data structures. Method. Smart data structures are represented by a logical vector and its derivatives in the form of truth tables and matrices. The test map is a matrix whose coordinates are determined by the combinations of all logical faults that are tested on the binary sets of the comprehensive test. The construction of the test map is focused on the architecture of in-memory computing based on read-write transactions, which makes the simulation mechanism economical in terms of simulation time and energy consumption due to the absence of a central processor. A logical vector as a single component of input data does not require synthesis into a technologically permitted structure of elements. Synthesis of smart data structures based on four matrix operations creates a fault test map like addresses for any logic. Results. Deductive matrix vectors are effectively used to model faults as addresses in digital structures of any configuration, including convergent branches and feedback loops. The resulting test map is used to find the minimum fault-checking test of the input variables. The proposed fault simulation mechanism technologically easily fits into the architecture of in-memory computing and uses only read-write transactions. The vector logic engine can also be used to test graph structures that are described by a truth table or a logical vector. The truth table addresses used for fault simulation are effectively used for processorless processing of large data in the in-memory computing architecture. Conclusions. Scientific novelty – a vector-logic in-memory computing mechanism for building a test map is proposed, characterized by the construction of intelligent data structures that reset the fault modeling algorithm. The proposed mechanism has no analogues in the design & test industry in terms of simplicity and predictability of data structure sizes and the absence of a test set modeling algorithm. The practical significance is determined by the application of the mechanism for testing logical functionalities of any complexity to solve verification tasks. Prospects of the research – increasing the object of diagnosis to the scheme, i.e. building a test map of the scheme logical structure.

Cited by 1Open access

Behavioral-level fault simulation

Sumit Ghosh · IEEE Design & Test of Computers · 1988

An approach to fault simulation is presented in which behavioral fault models represent complex failures in VLSI designs. Errors are deliberately introduced into the description of a design that contains no faults. These errors can be fault values of variables that represent state or timing parameters, a faulty description that is substituted for part of the good description, or a combination of these. The algorithm guarantees accurate results by deferring the output assignments. The approach can also be used to detect and discard inconsistent output assignments. The algorithm has been implemented in Stanford University's Sable simulator using the Adlib behavioral modeling language.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 30

Hierarchical delay fault simulation

C.P. Ravikumar, Atul K. Mittal · 1999

Increasingly, VLSI systems are being designed using macro blocks and predesigned cores. Since the clock rate at which these circuits operate is steadily increasing, it is important to perform delay testing on modern VLSI chips and systems. Algorithms for delay test generation and delay fault simulation are known to be compute-intensive. Many of these algorithms require gate-level descriptions of circuits which are difficult to generate and may be even impossible to provide when the designer has made use of predesigned cores. Hierarchical testing appears to be an attractive alternative in such cases. Tests generated for logic blocks may be reused to generate tests for larger systems comprising of the logic blocks, hence reducing the total effort in test generation. Tests show in this paper that the computational effort spent in fault simulation can also be reduced using a hierarchical approach. The simulator HIDEFS described in this paper exploits the modular nature of the circuit to save on the memory requirement as well as execution time requirement of fault simulation.

Cited by 1

Wind Turbine Fault Simulation

Qiu Yingning, Yanhui Feng, Sun Juan · 2013

Due to its complex design and stochastic environment that it is exposed to the ultimate symptom exhibited by a wind turbine with malfunction varies. It is a challenge to understand wind turbines' failure mechanism and the root causes which is because it is an integration system with both mechanical and electrical components. To understand the effect of degraded gearbox transmission efficiency to wind turbine system, a simulation model is developed to observe variation of rotor torque, generator torque, pitch angles. A wind turbine system dynamic response of output power is compared with the situation of a healthy turbine. It shows that for a wind turbine with degraded gearbox, increase of rotor torque and detectable pitch angle variations are obtained at above rated wind speed range and decreasing generator torque is observed at below rated wind speed range. Though gearbox degraded efficiency has no significant effects to system dynamic response, a lower power output should be observed at below rated wind speed range of power curve. The result obtained in this paper is useful for effective algorithm development of wind turbine fault detection.

Cited by 5

Logic-Level Fault Simulation

Raimund Ubar, Jaan Raik, Maksim Jenihhin et al. · Computer science foundations and applied logic · 2024

Cited by 0

SoK: Assisted Fault Simulation

Asmita Adhikary, Ileana Buhan · Lecture notes in computer science · 2023

Cited by 3Open access

Wind Turbine Fault Simulation

Yingning, Qiu, Juan, Sun, Yanhui, Feng · 2014

Cited by 0Open access

VHDL Fault Simulation for

Marcelino B. Santos, J. P. Teixeira, F. Celeiro et al. · 1996

For high quality VLSI products, exhibiting very low escape rates, defect-oriented testing becomes mandatory. The design activity is more and more supported by hardware description languages, like VHDL; hence, the testing activity needs to follow this trend. In this paper, a VHDL-based methodology for test preparation of digital ICs is proposed, and a new set of tools for defect-oriented VHDL fault simulation are presented, using a commercial VHDL simulator. The proposed methodology is also shown to be effective in supporting realistic fault diagnosis. Simulation results for benchmark circuits are presented. 1.

Cited by 0

Data parallel fault simulation

M.B. Amin, B. Vinnakota · 2002

Fault simulation is a compute intensive problem. Data parallel simulation on multiple processors is one method to reduce fault simulation time. We discuss a novel technique to partition the fault set for data parallel fault simulation. When applied statically, the technique can scale well for up to eight processors. The fault set partitioning technique is simple, can itself be parallelized, and can be implemented with extreme ease. Therefore, the technique can be used on a low cost parallel resource, such as a network of workstations.

Cited by 8

On distributed fault simulation

T. Markas, M. Royals, N. Kanopoulos · Computer · 1990

The authors examine the computational aspects of fault simulation of digital circuits and address issues related to the efficient partitioning of a fault simulation task to a number of subtasks assignable for execution to the nodes of a distributed system. They review the basic concepts involved in the operation of fault simulation. They describe the implementation of a distributed fault simulation facility, called DFSim, using a heterogeneous local area network consisting of a number of workstations with different computing resources and different versions of Unix operating systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 20

Laser-Induced Fault Simulation

Feng Lu, Giorgio Di Natale, Marie-Lise Flottes et al. · HAL (Le Centre pour la Communication Scientifique Directe) · 2013

International audience

Cited by 12Open access

Accelerated transition fault simulation

M. Schultz, F. Brglez · 1987

This paper presents a new and an effective approach to fault simulation of transition faults in combinational or scan - based logic. An experiment with a set of benchmark circuits demonstrates the efficiency of the approach, achieved by combining a very fast single stuck - at fault simulation algorithm with a quasi - static definition of a transition fault. Tests that cover transition faults are becoming increasingly important as they also provide a cover for most typical transistor stuck - open faults in CMOS.

Cited by 65