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article · Procedia Engineering · 2011

Speeding up Fault Simulation using Parallel Fault Simulation

Jiahua Fan, Zhifeng Zhang

Cited by 2Open access

Abstract

In this paper, a novel approach is introduced on accelerating the fault simulation speed on field programmable gate array (FPGA). The approach is based on parallel simulation methodology. More than one faulty circuit is handled in the fault simulation system, but the relative area overhead is low and it will accelerate the simulation process. A new metrics – Speedup relative to the Ratio of Hardware Overhead (SRHO) is introduced, by which the experimental results are evaluated. Experimental results in terms of simulation time, hardware overhead and SRHO for ISCAS-85 benchmark circuits are compared to a previous work to show its advantage.

Cite this paper

APA 7

Fan, J., & Zhang, Z. (2011). Speeding up Fault Simulation using Parallel Fault Simulation. Procedia Engineering, 15, 1817–1821. https://doi.org/10.1016/j.proeng.2011.08.338

MLA 9

Fan, Jiahua, and Zhifeng Zhang. “Speeding up Fault Simulation using Parallel Fault Simulation.” Procedia Engineering, vol. 15, 2011, pp. 1817–21, https://doi.org/10.1016/j.proeng.2011.08.338.

Chicago

Fan, Jiahua, and Zhifeng Zhang. 2011. “Speeding up Fault Simulation using Parallel Fault Simulation.” Procedia Engineering 15: 1817–21. https://doi.org/10.1016/j.proeng.2011.08.338.

Harvard

Fan, J. and Zhang, Z. (2011) ‘Speeding up Fault Simulation using Parallel Fault Simulation’, Procedia Engineering, 15, pp. 1817–1821. Available at: https://doi.org/10.1016/j.proeng.2011.08.338.

BibTeX
@article{fan2011speeding,
  title = {{Speeding up Fault Simulation using Parallel Fault Simulation}},
  author = {Fan, Jiahua and Zhang, Zhifeng},
  journal = {Procedia Engineering},
  volume = {15},
  pages = {1817--1821},
  year = {2011},
  doi = {10.1016/j.proeng.2011.08.338}
}

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