D.W. Lloyd, Jim Garside, D.A. Gilbert · 2003
Although a large number of asynchronous microprocessors have now been designed, relatively few have attempted to handle memory faults. Memory faults create problems for the design of any pipelined system which are exacerbated by the non-deterministic nature of an asynchronous processor. This paper describes these problems as encountered in the design of asynchronous ARM processors and discusses their specific solutions in the AMULET3 processor. Different mechanisms were used, as expedient, to maintain coherency for the various state-holding elements within the processor; these include register renaming and history buffering in addition to resource locking.
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D. Mesples, Pier G. Bargellini, Marcus Nilsson et al. · 2010
Mitigating the effects of Single Event Upsets (SEU) is critical to ensuring spacecraft safety in low earth orbits. The memory of the Central Communications Unit on Envisat, launched in March 2002 for a nominal life of 5 years, is protected by EDAC ensuring that any single bit flip identified during memory read instructions is corrected prior to usage by the processing unit. The memory is divided into two blocks (prime and redundant), each consisting of three pages. A memory scrubbing task runs in the background to correct the contents in the memory, and reports periodically the number of corrected SEUs. In November 2006, the memory scrubbing task began reporting SEUs at a very high rate which lead to a diagnosis of permanently faulty memory areas. Alas the limitations in the data available in the scrubbing report prevented assessment of the full extent of the problem. Fortunately, the internal prime memory block redundancy could be activated, masking the problem, and provided time for the development of a diagnostic routine. A similar behavior was then observed in another prime memory page in December 2007 while no further internal prime memory redundancy was available. The new diagnostic routine was used to obtain a detailed assessment of the affected memory areas. Furthermore, the memory fault statistics delivered by the scrubbing were no longer usable, the report being flooded by the permanent errors. The permanently corrupted memory areas also increased the risk of double event upset occurring which would have led to a mission interruption. A permanent swapping of the prime and the redundant memory blocks mitigated this risk, but at the cost of a potential loss in memory redundancy in case of an SEU occurring in the corrupted area. An extension to the Envisat operational lifetime was under discussion at the time of the second memory page anomaly and it was clear that failure to recover some memory redundancy could jeopardize approval. This was achieved by 1/modifying the Failure Detection Isolation and Recovery (FDIR) behavior in case of a double bit flip detection in redundant memory and, 2/improving the scrubbing task to make it tolerant to permanent errors. This paper presents the lessons learned from the Envisat prime memory anomalies and provides recommendations to the design of future LEO spacecraft data handling subsystems.
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Е.С. Лепёшкина · Modelirovanie, optimizaciâ i informacionnye tehnologii. · 2024
Рассмотрена проблема множественных сбоев, образующихся в микросхемах памяти бортовой аппаратуры космических аппаратов в результате воздействия отдельных ядерных частиц космического пространства. Обзор литературных источников показал, что опасность множественных сбоев реальна и будет увеличиваться по мере уменьшения технологических норм проектирования электронной компонентной базы. Двойные множественные сбои являются в настоящее время наиболее актуальной угрозой, так как их появление вызвано заряженными частицами с относительно небольшой энергией. Двойные сбои могут быть смежными и несмежными. Смежные двойные сбои вызваны одномоментным действием одной ядерной частицы. Несмежные сбои – это результат накопления однократных сбоев, произошедших в разное время в разных запоминающих ячеек одного слова памяти. При определенных условиях можно избежать появление двукратных несмежных ошибок. Для защиты от двойных смежных ошибок применимы коды для их исправления. Эти коды являются относительно новыми и обобщённое описание их построения отсутствует. Данные коды гарантировано исправляют однократные ошибки и двукратные смежные, но имеют существенную вероятность ошибочного исправления несмежной двойной ошибки. При переходе к практическому использованию для этих кодов необходимо определить требования к виду проверочной матрицы, найти общий алгоритм их построения для разной длины слова памяти при малой избыточности и высокой производительности при условии, что к корректирующим способностям кода предъявляются требования обнаружения и исправления только одиночных и двойных смежных ошибок и никаких дополнительных. The problem of multiple faults in the memory chips of on-board equipment of spacecraft as a result of the impact of individual nuclear particles in outer space is considered. A review of the literature showed that the danger of multiple failures is real and will increase as technological standards for the design of electronic components decrease. Double multiple faults are currently the most pressing threat, as they are caused by charged particles with relatively low energies. Double faults can be adjacent or non-adjacent. Adjacent double faults are caused by the simultaneous action of a single nuclear particle. Non-adjacent faults are the result of the accumulation of single failures that occurred at different times in different storage cells of the same memory word. Under certain conditions, the occurrence of double non-contiguous errors can be avoided. To protect against double adjacent errors, correcting codes are used. These codes are relatively new and there is no general description of their construction. These codes are guaranteed to correct single errors and double adjacent errors, but have a significant probability of erroneously correcting a non-adjacent double error. But when moving to practical use, it is necessary to determine the requirements for the type of check matrix for these codes, to find a general algorithm for their construction for different memory word lengths, with low redundancy and high performance, provided that the correcting abilities of the code are subject to the requirements of detecting and correcting only single and double adjacent errors and no additional ones.
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Chlebus Gambin, B. S. Chlebus, A. Gambin et al. · 2007
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Leszek Gąsieniec, Piotr Indyk · Lecture notes in computer science · 1997
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Danny Dolev, David Maier, Ilarry Mairson et al. · 1984
Article Correcting faults in write-once memory Share on Authors: Danny Dolev View Profile , David Maier View Profile , Ilarry Mairson View Profile , Jeffrey Ullman View Profile Authors Info & Claims STOC '84: Proceedings of the sixteenth annual ACM symposium on Theory of computingDecember 1984 Pages 225–229https://doi.org/10.1145/800057.808685Online:01 December 1984Publication History 2citation230DownloadsMetricsTotal Citations2Total Downloads230Last 12 Months2Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access
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Mark McCann · 2007
As computational systems scale to arbitrarily large sizes, and as they are expected to function reliably for arbitrary lengths of time, there are certain realities of the physical world that can not be ignored in the design and modeling of computational systems. For example, considerations for the delivery of power and removal of heat seem to limit the system to a two-dimensional surface. Additionally, it can be argued that all of the following restrictions are desirable and reasonable: there is a finite variety of components, no components (or external agents) are immune to failure, and components can communicate only with a bounded number of other components over a bounded distance. A very general model, with a reasonable ability to capture many of these features, is that of a cellular automaton. We extend the widely studied model of transient faults (which occur independently at different places and different times) in cellular automata to consider manufacturing faults (which occur independently at different places, but affect cells for all time). Although a well known monotone binary transition rule (known as Toom’s Rule) in two dimensions can remember a bit (that is, the system can be used to preserve a single Boolean value for all time with probability one) in the presence of transient faults, we show that no monotone binary transition rule in two dimensions can remember a bit when both manufacturing faults and transient faults are present. On the other hand, we give a monotone binary transition rule in three dimensions that can remember a bit in the presence of both manufacturing faults and transient faults. (By adding one or two further dimensions, one can reduce the problem of performing an arbitrary computation reliably to the problem of remembering a single bit.) We also study cellular automata that are based on hyperbolic (rather than Euclidean) tessellations (including infinite regular trees), and we completely classify the cases in which majority voting among all nearest neighbors can tolerate manufacturing faults and/or transient faults. iii
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A.J. van de Goor, P.C.M. van der Arend, G.-J. Tromp · 2005
A memory array is considered a collection of RAM chips interconnected via data lines, row-select lines and wordselect lines. The stuck-at and bridging fault models are assumed for those lines. For each type of line an algorithm to locate the fault, in the presence of possible faults in thle other lines and possible faults in the RAM chips, is presented. The algorithms are proven to be correct and an analysis of their robustness (insensitivity to other faults in the imemory anay) is given. The sequence in which the tests have to be performed is determined. Index Terms .. RAM testing, board testing, bridging faults, fault location.
Cited by 4
D. Ronga, Eric Faehn, P. Girard et al. · 2025
Modern integrated circuits such as System-On-Chip (SoC) require substantial memory capacity to operate. To ensure the reliability of these computing systems, high memory quality must be maintained, making continuous improvements in memory testing essential. To prevent any limitation from the widely used functional memory test strategy, regarding the context of ever-increasing complexity in memories, structural testing has been proposed as an effective method for improving memory testing. Structural testing methodologies requiring a digital memory modeling has enabled the use of powerful tools from the digital domain, such as Fault Simulators (FS) and Automatic Test Pattern Generators (ATPG) in memory testing. Leveraging digital memory modeling, this work proposes HCM (Hardware Context Monitoring), a modular methodology for modeling complex memory faults (i.e. dynamic and multi-cell dynamic) within a digital test environment. HCM enables the evaluation of test algorithms in terms of their ability to detect complex faults, and it supports fault-oriented, optimized, and automated test pattern generation. Experimental results using dRDF case study while considering stress effects in the memory array demonstrate the effectiveness of HCM in assessing the fault coverage capabilities of various March algorithms.
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Microelectronics Reliability · 1981
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Daniel Mesples, Magnus Nilsson, Michel Horblin · SpaceOps 2010 Conference · 2010
Cited by 1Open access
Microelectronics Journal · 1982
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Ram Kumar Δ, Florin Sultan, Kiran Nagaraja et al. · 2008
Typical sensor nodes use resource constrained micro-controllers where user level applications, operating system components, device drivers, etc., reside within a single address space with no form of memory protection. A programming error in an application can easily corrupt the state of the operating system and other software components on the node. To protect against such errors, we propose a two tier software scheme that achieves: (i) coarse grained memory protection of the operating system state, and (ii) fine grained detection of memory corruption and subsequent recovery of application components. Coarse grained memory protection is provided by creating and enforcing an application fault domain that restricts the memory accesses made by an application to a portion of the address space. The operating system state is stored outside the application fault domain and is therefore protected from memory corruption. Fine grained memory corruption detection and recovery is provided within the application fault domain. Memory corruption faults are detected by a run-time integrity verifier. The associated recovery mechanism restarts only the affected application module thereby achieving a low recovery time. We have implemented our scheme in the SOS operating system and tested it on a network of MicaZ nodes. Our evaluation shows that the scheme effectively handles memory corruption faults while having negligible impact on the performance and lifetime of real sensor network systems. 1
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Jürgen Dunkel · 2002
A modeling approach to investigating the interdependencies between memory faults and system performance is presented. Describing the program behavior by an independent reference model, the author develops a fault occurrence model that depends on workload characteristics such as task sojourn times, the number of page references, and the number of page faults. Determining the probability that a fault is detected at a page test, the author quantifies the workload required for fault handling. Using a queuing network in a stationary analysis, he evaluates the average performance decrease caused by memory faults. The interdependencies between performance and reliability quantities are described by a set of nonlinear equations. An iterative method for evaluating the model is given. The results of some experiments demonstrate that the performance decrease caused by memory error depends on system workload and operating system characteristics.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 9
Alan Roger Klayton, W. A. Barrett, Arthur I. Larky · 1971
Algorithms for the detection and diagnosis of faults in semiconductor random-access, word-organized memory systems are presented and evaluated. The memory system is conceptually partitioned into four major elements to facilitate analysis. During the testing of each element, previously tested elements are assumed to be fault-free, but untested elements may contain multiple faults. The problem of fault masking and interaction between the major elements of the system is investigated and considered in the development of the algorithms.
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A.J. van de Goor, Georgi Gaydadjiev · IEE Proceedings - Circuits Devices and Systems · 1997
Short and efficient memory tests is the goal of every test designer. To reduce the cost of production tests, often a simple test which covers most of the faults, e.g. all simple (unlinked) faults, is desirable to eliminate most defective parts; a more costly test can be used thereafter to eliminate the remainder of the bad parts. Such a test-cost efficient approach is used by most manufacturers. In addition, system power-on tests are not allowed a long test time while a high fault coverage is desirable. The authors propose a new realistic fault model (the disturb fault model), and a set of tests for unlinked faults. These tests have the property of covering all simple (unlinked) faults at a very reasonable test time compared with existing tests.
Cited by 37
A.J. van de Goor, Georgi Gaydadjiev, V. N. Yarmolik et al. · 2002
This paper introduces a test which can detect all simple faults as well as all linked faults, involving an arbitrary number of simple faults.
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LIU Ruitao,CHEN Zuoning · SHILAP Revista de lepidopterología · 2019
Based on the massive amount of statistical data about memory faults on Sunway TaihuLight and Sunway BlueLight supercomputers,the memory failure time model for Petascale supercomputers is built.By sequential rule mining,the sequential pattern of memory failures is analyzed and the correlation relationship between memory failure sequences and the following memory failure on CPU nodes is found.The characteristics of memory faults and failures on parallel applications are studied by the co-analysis method.Results show that computing-memory-I/O intensive applications have large impact on memory faults while the type of applications has limited impact on memory failures,which,however,may have correlation relationship with the reliability of memory chips.
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Mat Isa, Masnita · Universiti Putra Malaysia Institutional Repository (Universiti Putra Malaysia) · 2012
The fast growing of technologies has enabled the Static Random Access Memories (SRAMs) to contain higher density of cell array which make it prone to be affected by defects. This factor contributes to challenges faced in the area of memory testing. Functional test is a standard testing procedure to determine the functionality of the memory by performing a sequence of read write operations to detect faults. March tests are widely used during functional testing due to its higher fault coverage and less time complexity. March tests are developed based on functional fault model (FFM) such as stuck-at faults (SAFs), transition faults (TFs) and coupling faults (CFs). Recent March tests have incorporate a diagnostic capability that enables faults not only to be detected but also distinguished. The diagnosis capability of March tests are verified based on generated fault syndromes dictionary that correspond to the detection of targeted faults during read operations. However, existing March tests with diagnostic capability were not able to distinguish between SAFs and TFs. Therefore, this thesis proposed a new two phase algorithm based on March tests to specifically distinguish the two faults. The fault syndrome based on read operations of the proposed algorithm is generated to determine its diagnostic capability. The SAFs and TFs are able to be distinguished from each other when different syndromes are generated for each fault. The fault syndromes are then validated by simulating the sequence of propose algorithms on defect free test circuit and test circuit that contains defects mapped to SAFs and TFs. The test circuit consists of write circuitry, six transistors (6T) SRAM cell and sense amplifier circuit. The simulation also includes the testing of MATS++ and March C- algorithms in order to verify the circuit functionality and validate the types of defects belong to both SAFs and TFs. Findings shows that the propose algorithm generates different fault syndromes for SAFs and TFs hence make them distinguishable. Results obtained from simulation validate the generated fault syndromes thus confirmed the ability of this algorithm to detect and distinguish between SAFs and TFs.
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Douglas M. Blough · 2002
Reconfiguration of memory arrays using spare rows and spare columns, a useful technique for yield enhancement of memories, is considered under a compound probabilistic model that shows clustering of faults. It is shown that the total number of faulty cells that can be tolerated when clustering occurs is larger than when faults are independent. It is shown that an optimal solution to the reconfiguration problem can be found in polynomial time for a special case of the clustering model. Efficient approximation algorithms are given for the situation in which faults appear in clusters only and the situation in which faults occur both in clusters and singly. It is shown through simulation that the computation time required by this algorithm to repair large arrays containing a significant number of clustered faults is small.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 25