Holger Scherl · Vieweg+Teubner eBooks · 2011
AbstractFor a long time, the performance of general-purpose processors could be improved by increasing clock frequency and instruction level parallelism (ILP). Nowadays, only diminished gains in performance can be reached by higher processor clock rates. This results from the difficulty to find enough parallelism in the instruction stream of a single process to keep higher performance processor cores busy. Another cause is the increasing gap between processor and main memory speed because the latency and the bandwidth of dynamic random access memory (DRAM) does not improve accordingly to processor operating frequencies. Finally, higher clock rates of generalpurpose processors lead to dramatically increased problems in manufacturing, system design, and deployment. These three arguments, commonly referred to as the ILP wall, the memory wall and the power wall, respectively, have constituted much of the motivation for the advent of multi-core processors during the last few years.KeywordsProjection ImageDynamic Random Access MemoryWork ThreadInstruction Level ParallelismStream SIMD ExtensionThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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O L. B. Ribeiro · 2010
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2008
Designing multi-threaded and multi-core processor architectures has become one of the most challenging projects for computer scientists in the last few years. But not only the design of such architectures for desktop computers, servers, or high performance computing (HPC) clusters has been investigated in a sophisticated manner, also in the area of embedded systems, researchers have started to investigate the possibilities of using the newly acquired knowledge to implement multi-core processors for embedded systems. Unfortunately, such streamlined computers bring a whole lot of constraints to the design of processor in general. Just to name some of them, scientists have to deal with less memory available, less possibilities to cool the evolving heat, and last but not least, the most important design criteria means to be that embedded systems cannot provide the integrated processors with the same amount of power as the above mentioned systems (like servers or HPC clusters). But these are only a few of the main problems scientists were faced with in the early days of processor design, especially the design of multi-core processors for embedded systems. This paper will give the reader a profound overview of the main architectural approaches, currently used in field implementations and they will also be discussed. Furthermore the reader will be presented some of the available real life implementations of the various architectural approaches, which will as well be discussed in detail by pointing out their assets and drawbacks. 1 1
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Andrea Manconi (566020), Alessandro Orro (28770), Emanuele Manca (566021) et al. · Figshare · 2015
<p>Multi-core processors as CPUs are devices composed of few cores with lots of cache memory able to handle a few software threads at a time. Conversely, many-core processors as GPUs are devices equipped with hundreds of cores able to handle thousands of threads simultaneously.</p>
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Ανδρεαδάκης, Γεώργιος · Eureka! Institutional Repository (Eureka!) · 2015
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Matthias Petschow · 2016
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Balaji Venu · arXiv (Cornell University) · 2011
Microprocessors have revolutionized the world we live in and continuous efforts are being made to manufacture not only faster chips but also smarter ones. A number of techniques such as data level parallelism, instruction level parallelism and hyper threading (Intel's HT) already exists which have dramatically improved the performance of microprocessor cores. This paper briefs on evolution of multi-core processors followed by introducing the technology and its advantages in today's world. The paper concludes by detailing on the challenges currently faced by multi-core processors and how the industry is trying to address these issues.
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Max Domeika · Elsevier eBooks · 2008
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Abualsoud Hanani, Michael J. Carey, Martin Russell · Computer Speech & Language · 2012
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Kun Tan, See Profile, He Liu et al. · 2016
All in-text\treferences\tunderlined\tin\tblue\tare\tlinked\tto\tpublications\ton\tResearchGate, letting you\taccess\tand\tread\tthem\timmediately.
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S. G. Elizarov, G. A. Lukyanchenko, Д С Марков et al. · PROGRAMMNAYA INGENERIA · 2017
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Guoping Xu · 2017
To improve computing performance for server systems, increase in the number of CPU cores is one of the primary design parameters, in addition to higher frequency and advanced process technology node adoption. CPU core count, size, physical distribution and power density on the processor die could have great impact on thermal and computing performance. A thermal analysis is performed to understand these effects with the modeling assumptions: 60 mm × 60 mm flip chip lidded package, single die at size of 25 mm × 25 mm and total power dissipation of 300W. The thermal model including package and heat sink is set up to analyze variables such as core count, distribution and power level/density. To keep the processor temperature from exceeding the junction limit, dynamic voltage and frequency scaling (DVFS) is commonly used. A method to correlate thermal and computing performance based on DVFS, is also explored when junction temperature hits the limit. The impact of multi-core processor design on thermal performance is translated into the impact on computing performance under thermal constraints. Thermal guidance on multi-core processor die floor plan to optimize computing performance is provided.
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Najem N. Sirhan · Zenodo (CERN European Organization for Nuclear Research) · 2018
This research paper aims at comparing two multi-core processors machines, the Intel core i7-4960X processor (Ivy Bridge E) and the AMD Phenom II X6. It starts by introducing a single-core processor machine to motivate the need for multi-core processors. Then, it explains the multi-core processor machine and the issues that rises in implementing them. It also provides a real life example machines such as TILEPro64 and Epiphany-IV 64-core 28nm Microprocessor (E64G401). The methodology that was used in comparing the Intel core i7 and AMD phenom II processors starts by explaining how processors' performance are measured, then by listing the most important and relevant technical specification to the comparison. After that, running the comparison by using different metrics such as power, the use of HyperThreading technology, the operating frequency, the use of AES encryption and decryption, and the different characteristics of cache memory such as the size, classification, and its memory controller. Finally, reaching to a roughly decision about which one of them has a better over all performance
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Meredydd Luff · 2013
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Johannes Singler · Repository KITopen (Karlsruhe Institute of Technology) · 2010
By providing parallelized versions of established algorithm libraries, we ease the exploitation of the multiple cores on modern processors for the programmer. The Multi-Core STL provides basic algorithms for internal memory, while the parallelized STXXL enables multi-core acceleration for algorithms on large data sets stored on disk. Some parallelized geometric algorithms are introduced into CGAL. Further, we design and implement sorting algorithms for huge data in distributed external memory.
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Suzanne M. Kelly, John P. VanDyke, Courtenay Vaughan · 2007
The XT3 Catamount Virtual Node (CVN) implementation was based on the dual processor support in ASCI Red’s [1] Cougar Light Weight Kernel Operating System. That solution was limited to no more than 2 virtual nodes per physical node. This paper describes the design for extending Catamount to support more CPUs per node. It identifies the areas needing modification and the selected resolution. Some preliminary performance results are provided.
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Andrew Whitehouse DeOrio · Deep Blue (University of Michigan) · 2012
Computer chips, the most complex artifacts ever made by man, are susceptible to problems with correct functionality due to their intricacy. Incorrect operation of silicon chips has lasting, and sometimes devastating, effects on computer systems and their manufacturers: from incorrect computation results, to security vulnerabilities affecting end users, to financial impact on the vendors. Furthermore, new chips are increasingly fragile, liable to break as the transistors that comprise them become small enough to be measured in atoms. A typical modern computer usually includes a single chip where many processors are connected by a communication medium. This communication medium, a new feature in modern chips, provides many opportunities for catastrophic errors, as it is a complex, unpredictable, unique component. The goal of this dissertation is to provide a new solution to ensure the correct operation of the communication medium in multicore processors, from the early stages of design to the end user. It addresses failures in several modes, and operates across the different phases of the verification process, integrating them into a cohesive framework. A key finding of this work is the synergy among verification phases, connected by a novel abstraction technique and multipurpose hardware and software. Simply put, it ensures that the design operates as intended. This approach to the development cycle accelerates, automates and extends the reach of the verification process, providing decreased occurrence of -- and increased resilience to -- failures. With this solution, the communication system of multi-core chips can operate free from errors.
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IRIS Research product catalog (Sapienza University of Rome) · 2016
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Sevin Fide · 2008
The quest for greater computational power is never-ending. Recently, the architectural trend has shifted from improving single-threaded application performance to improving multi-threaded application performance. Thus, multi-core processors have been increasingly popular. To achieve concurrent execution of threads on multi-core processors, applications must be explicitly restructured to exploit parallelism, either by programmers or compilers. However, conventional parallel programming models may introduce overhead due to synchronization and communications among threads in multi-threaded applications. This book presents three architectural optimizations to improve thread-based synchronization and communications support in multi-core processors. Register-Based Synchronization (RBS) uses hardware registers efficiently to provide synchronization support in multi-core processors. Prepushing is a software controlled data forwarding technique to provide communications support in multi-core processors. Software Controlled Eviction (SCE) improves shared cache communications by placing shared data in shared caches.
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Guoping Xu · 2006
A thermal model was developed to investigate the effect of multi-core microprocessor circuit layout on thermal performance. Die size of 20 mm times 20 mm and power dissipation of 200W were assumed in the model. A high thermal conductivity heat spreader of 50mm times 50 mm times 2 mm and air-cooled heat sink base of 100 mm times 100 mm times 5 mm were employed for the model. The study begins with single core chip layout. Several variables including CPU power level, local hot spot power density, hot spot location and hot spot size were evaluated in the simulation. Thereafter, thermal performance of a multi-core processor with multiple hot spots in a single chip was simulated at various distributions, hot spot sizes, and number of hot spots. Thermal performance comparison was made between single core and multi-core architectures on a single chip. Finally general thermal guidance is given for the circuit design
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