K. Yadaiah, Vijayalaxmi Biradar · International Journal of Recent Technology and Engineering (IJRTE) · 2019
Texas Instruments fabricated a single chip DM3730 processor with 45nm technology with improved performance. Less power consumption and imrpoved Graphics features are the key parametes of ARM architecture. DM3730 has 1GHz processor with 0.4mm pitch Package on Package. Design of effective system is facilitated by properly debugging the hardware and software. The system for detection of driver fatigue for its implementation requires coming in contact with the camera to capture driver image, speaker for warning messages, GSM module to disseminate SMS, mouse, internet, keyboarb, etc. for installing different packages. In this paper, DM3730 Processor is tested for different peripherals on Linux Platform.This paper is a part of research work on the project “Development of Non-Intrusive Driver Fatigue Detection &Alarming System to evade on road accidents” sanctioned under Early Career Research Award sponsored by Science & Engineering Research Board, Govt. of India, New Delhi at Vignan Institute of Technology & Science, Vignan Hills, Hyderabad.
Cited by 0Open access
Xiao Hu, Shuming Chen · 2007
On-chip trace system records run-time information of the embedded processor with special hardware to overcome the obstacle of non-intrusive debug and optimization of traditional techniques. This paper explores the mechanism, characteristics and applications of on-chip trace technique with TraceDo, an on-chip trace system of a multi-core SoC. The functions and structures of TraceDo are introduced, the working process of path trace is explained and the trace applications with two cases of debug and optimization are also discussed.
Cited by 3
Giovanni Busonera, Alessandro Forin, Neil Pittman · 2007
eBug is a debugging solution for software developed on the eMIPS dynamically-extensible processor. The offchip portion of eBug is an application that performs tasks that would be too expensive or too inflexible to perform in hardware, such as implementing the communication protocols to interface to the client debuggers. The on-chip hardware portion of eBug is realized with a new approach: rather than being built into the base pipelined data path, it is a loadable logic module that uses the standard Extension interface of the processor. This accomplishes the three goals of area minimization and reuse, security in a general purpose, multi-user environment, and open-ended extensibility. When not in use, eBug is simply not present on the chip and its area is therefore reused. eBug solves the security issues normally created by a hardware-level debug module because only the process that owns the eBug Extension can be affected by a debugging session. As an Extension, eBug is not compiled into the basic processor design and this makes it easy to add new features without affecting the core eMIPS design. Leveraging the high-visibility extension interface of eMIPS, eBug can realize arbitrarily complex features for high-level monitoring. In this paper we describe how we transparently added hardware watchpoints to the initial, simpler design. It is also possible to interface eBug with other eMIPS extensions such as those generated by P2V to improve its capabilities. eBug was written in Verilog and is usable both with the Giano system simulator and on the Xilinx ML401 FPGA board.
Cited by 0
Paul B. Thistlewaite, Chris Johnson · 1993
The new class of MIMD computers with a thousand or more processors (kilo-processor machines) is over-reaching the available program development support tools. One such machine is the Fujitsu ap1000. The LERP project at the Australian National University aims to assist the ap1000 programmer with essential monitoring and debugging tools. LERP is based on off-line analysis and replay of an event trace which includes both low level system events and user-defined events. In this paper we address the issues of extracting humanly usable information from large event traces with a new compound event analysis tool, suited to machines of the ap1000 scale. Keywords: debugging, compound events, kilo-processors, event trace analysis 1 Introduction The Fujitsu ap1000 is a pioneering member of a class of MIMD wormhole message-passing machines with many hundreds of processors (each of which is a general purpose microprocessor with significant speed and memory in its own right), connected by three comm...
Cited by 3
Shan Gao, Wan’ang Xiao, Zhenghong Yang et al. · Journal of Physics Conference Series · 2021
Abstract In order to improve the efficiency of on-chip debugging, a fast on-chip debugging design is proposed, which adopts JTAG interface and is applied in RISC-V processor. In this paper, we extend some debugging instructions, effectively reducing data entry by operating the debugging bus directly, and realize the breakpoint, pause, single step, et al., providing conveniences for the development and debugging of the software system.
Cited by 2Open access
Swethasri Kavuri · International Journal of Scientific Research in Computer Science Engineering and Information Technology · 2023
This comprehensive research paper explores cutting-edge debugging techniques for multi-processor communication in 5G systems. As 5G networks continue to evolve and expand, the complexity of multi-processor communication introduces unique challenges in system debugging and optimization. This study examines various advanced debugging methodologies, including distributed tracing, time-travel debugging, AI-assisted anomaly detection, and hardware-assisted techniques. The research also delves into real-time debugging protocols, security considerations, and performance analysis of these debugging solutions. By synthesizing current literature and industry practices, this paper provides valuable insights into the state-of-the-art debugging approaches for 5G systems and outlines future research directions in this critical field.
Cited by 27Open access
Haskell P · Science and Technology Facilities Council · 1977
Cited by 0
C. A. Witschorik · Software Practice and Experience · 1983
Abstract Real‐time computer systems can be difficult to test when their timing characteristics influence the occurrence of problems. Because of this, tools for debugging real‐time systems must account for the interference that they produce in the system they are monitoring. The debugging monitor for the Bell System 1A processor is an example of just such a tool. This paper examines the 1A processor debugging monitor, focusing on the division of the monitor into three separate devices: a hardware monitor that allows autonomous debugging; a resident monitoring program that allows debugging with a minimal interference to normal timing; and a separate mini‐computer monitor that offers extended capability at the expense of unrestricted interference.
Cited by 11
Haskell, P · CERN Document Server (European Organization for Nuclear Research) · 1977
Cited by 0
Hanssel Enrique Morales Norato · Universidad Industrial de Santander · 2021
Alcanzar un bajo consumo de energía es uno de los desafíos críticos, en los nodos de sensoresde Internet de las cosas (loT) que funcionan con baterías de bajo costo. Estos nodos suelen estarcoordinados por un procesador que recopila, opera y transmite datos desde múltiples sensores ala nube. Los procesadores de loT deben administrar cargas de trabajo caracterizadas por ráfagasintermitentes de operaciones de procesamiento intensivo mezcladas con períodos prolongados debaja actividad. La minimización de la potencia dinámica a través de microarquitecturas de baja conmutación ha sido el foco de soluciones recientes. Aunque esto puede conducir a una baja eficienciade ejecución aumentando el tiempo de ejecución por lo tanto, conduciendo a un alto aumento de laenergia consumida. Este trabajo explora la adición de técnicas de aceleración de bajo costo paramejorar la eficiencia computacional en el diseño de Arcabuco, un procesador en orden de un soloproblema basado en RISC-V | / IM. Lo que logra 2.7 CoreMark/MHz y 1.13 DMIPS/MHz, con unconsumo de energía de 84.46/¿.W/MHz. Proporcionando una solución alternativa a las aplicaciones de bajo consumo de energía.
Cited by 0Open access
Paulina Rico-García · Revista de Computo Aplicado · 2023
RISC-V processors are an open source ISA (Instruction Set Architecture), which means that anyone can design and modify them to meet the specific objectives of any development. Thanks to the flexibility it brings with it, it is possible to add a debugging and programming logic unit to this processor to get a real sense of how the processor works, a unit that will be key to identifying errors during the design of the processor, as well as errors that may occur during the manufacturing process. This article presents the methodology used to incorporate hardware that allows the processor to be debugged, using the IEEE 1149.1 standard as a reference
Cited by 1Open access
Shan Gao, Dehua Wu, Wan'ang Xiao et al. · Greater South Information System · 2022
An on-chip debugging method based on the RISC-V processor is introduced, which simplifies the complicated debugging operation into instructions and improves the debugging efficiency effectively. The method adopts a JTAG interface to realize the debugging functions of the processor, such as running control, software breakpoint, hardware breakpoint and single-step execution. The method was verified by simulation at the RTL level, and the logic synthesis was carried out in SMIC 180nm process library.
Cited by 0Open access
Shan Gao, Dehua Wu, Wan’ang Xiao et al. · MATEC Web of Conferences · 2022
An on-chip debugging method based on the RISC-V processor is introduced, which simplifies the complicated debugging operation into instructions and improves the debugging efficiency effectively. The method adopts a JTAG interface to realize the debugging functions of the processor, such as running control, software breakpoint, hardware breakpoint and single-step execution. The method was verified by simulation at the RTL level, and the logic synthesis was carried out in SMIC 180nm process library.
Cited by 0Open access
Thomas Gross, Susan Hinrichs · 1992
To understand or improve the execution behavior of a program on a parallel system, it is often necessary to consider the interaction between the processors in the system. Since communication is important for all parallel programs, obtaining information about the inter-process communication of the program is an important aspect of understanding program execution. If the user's concern is the performance of the parallel program, then the user must be able to capture the dynamic aspects of interprocessor communication. Unfortunately, timing information about inter-processor communication is often not easy to obtain. Building a special-purpose hardware performance monitor is too costly in most scenarios, and the use of VLSI to integrate communication and computation on a single component often provides only a few externally visible measurement points. A software monitor on the other hand is often too slow to allow execution of the monitored program without serious perturbation. Although th...
Cited by 0
Shan Gao, Dehua Wu, Wan'ang Xiao et al. · Greater South Information System · 2022
An on-chip debugging method based on the RISC-V processor is introduced, which simplifies the complicated debugging operation into instructions and improves the debugging efficiency effectively. The method adopts a JTAG interface to realize the debugging functions of the processor, such as running control, software breakpoint, hardware breakpoint and single-step execution. The method was verified by simulation at the RTL level, and the logic synthesis was carried out in SMIC 180nm process library.
Cited by 0Open access
Corsetto, D., Shao, Beibei, Istituto Nazionale di Fisica Nucleare, Turin (Italy) · OpenGrey (Institut de l'Information Scientifique et Technique) · 1988
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Tang Jun-qi · 2006
Parallel Implementation method of procedure is very important in loose coupling multi processor,how person who walk abreast in procedure carry on thus reasonable debugging confirm person who run side by side quality of implementation method have heavy realistic meaning very.The article has proposed debugging the tactics and several kinds of debugging methods.
Cited by 0
Zhao Wang, Pengfei Xu, Li Zhou et al. · 2024
Verifying CPU chips is a highly challenging task due to intricate hardware design and complex operating system software. Identifying and debugging software execution errors within an operating system environment can be time-consuming, sometimes taking several months to resolve. When running a program in an operating system environment, a segmentation fault is standard error that occurs. In the past, only the software aspect of this issue was analyzed. However, this paper delves into the mechanism of segmentation fault from both software and hardware perspectives. It presents a segmentation fault flow view from the software and hardware coordination perspective and proposes two methods for debugging segmentation faults from both hardware and software perspectives. To validate the effectiveness of these methods, an experimental environment was built based on the open-source RISC-V processor C906. Experimental verification was conducted on common segmentation fault scenarios like an invalid page table and page read/write permission mismatch. The experimental results demonstrate that the proposed methods can acquire the exception cause, physical address, and stack information of the segmentation fault, effectively accelerating the debugging of the segmentation faults.
Cited by 0
Mattis Paul Jaksch, Jan Budroweit, Ferdinand Stehle · Zenodo (CERN European Organization for Nuclear Research) · 2022
Caches are vitally important for the performance in modern CPUs. But they also bear great potential for malfunction when put under irradiation. Hence, trade-offs have to be made for either performance or reliability.In this paper we present a deeper insight on the CPU caches, their influence in a running operating system and possible reasons for their malfunction. Therefore, a proton source with 230 MeV was used to target an ARM Cortex A9 in a Zynq-7000, running an embedded Linux with KGDB. As a result, we tested three different cache configurations, which showed three distinct error cases. This can help to improve the understanding of system malfunctions due to radiation and build useful mitigation techniques.
Cited by 7Open access
С. А. Чекмарев, В Х Ханов · IOP Conference Series Materials Science and Engineering · 2015
The paper presents an on-chip debugging method for the injection of single faults in the processor cores of systems-on-chip. The method consists in the placement of faults injection infrastructure in a system-on-chip as an intellectual property core. This simplifies the fault injection environment, reduces delays injection and improves the performance, as well as allows doing long autonomous campaign for injection of faults without the use of external devices.
Cited by 5Open access