Karthika K, Tarappa, Manoj H P et al. · Zenodo (CERN European Organization for Nuclear Research) · 2025
The rapid growth of embedded systems and digital computing demands processor architectures that are both efficient and hardware-friendly. The Microprocessor without Interlocked Pipeline Stages (MIPS) architecture, a classic RISC model, offers a streamlined instruction set and modular design that makes it ideal for academic study and real-time hardware implementation. This project presents the design and FPGA-based implementation of a 32-bit MIPS processor, developed using Verilog HDL and verified through industry-standard simulation and synthesis tools. The architecture integrates essential components including the Program Counter, Instruction Memory, Register File, ALU, Control Unit, Data Memory, Multiplexers, and Sign Extension blocks, forming a complete datapath capable of executing arithmetic, logical, memory access, and branching instructions. the design follows a systematic methodology beginning with RTL modelling of core functional units, followed by integration into a multi-stage datapath and verification using Xilinx toolchains.
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Steven M. Parmley, Steven M. Parmley, Steven M. Parmley et al. · 1997
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Karthika K, Tarappa, Manoj H P et al. · Zenodo (CERN European Organization for Nuclear Research) · 2025
The rapid growth of embedded systems and digital computing demands processor architectures that are both efficient and hardware-friendly. The Microprocessor without Interlocked Pipeline Stages (MIPS) architecture, a classic RISC model, offers a streamlined instruction set and modular design that makes it ideal for academic study and real-time hardware implementation. This project presents the design and FPGA-based implementation of a 32-bit MIPS processor, developed using Verilog HDL and verified through industry-standard simulation and synthesis tools. The architecture integrates essential components including the Program Counter, Instruction Memory, Register File, ALU, Control Unit, Data Memory, Multiplexers, and Sign Extension blocks, forming a complete datapath capable of executing arithmetic, logical, memory access, and branching instructions. the design follows a systematic methodology beginning with RTL modelling of core functional units, followed by integration into a multi-stage datapath and verification using Xilinx toolchains.
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Bodhisatwa Sarker, Eckhard Grass, Koushik Maharatna · ePrints Soton (University of Southampton) · 2002
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Jagannath Keshava And · 1999
This paper discusses the implementation tradeoffs of the Pentium III processor. The Pentium III processor implements a new extension of the IA-32 instruction set called the Internet Streaming Single-Instruction, MultipleData (SIMD) Extensions (Internet SSE). The processor is based on the Pentium Pro processor microarchitecture.
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Tey, Jing Kai · DR-NTU (Nanyang Technological University) · 2024
RISC-V is an open-standard Instruction Set Architecture (ISA), and RV32I is a \nsubset of RISC-V instructions. The simplicity of RV32I makes it ideal for educational \npurposes. \nThis project is to implement a RISC-V (RV32I) Processor (softcore with a simple \nHarvard architecture) on Nexys A7 Xilinx Artix®-7 FPGA using Verilog. Different \nprocessor micro-architectures, single-cycle, multi-cycle and multi-stage pipeline (with \nstatic branch predictor) are explored in this project. The design is based on Hardware \nDescription Languages (HDL) - Verilog and IDE - Vivado Design Suite. In addition \nto the RV32I processor, essential modules such as universal asynchronous \nreceiver/transmitter (UART Tx and Rx), seven-segment display, and other device \nmodules were developed. \nA basic loader firmware in C was also developed to provide the capability to load \ncustom user programs and provide software access to the mapped devices. \nThe complete implementation of RV32I on Nexys A7 FPGA board offers valuable \ninsight into computer architectures, integrating different knowledge across the years \ninto a comprehensive understanding.
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P. Saiprathyusha, C. Chandrasekhar · ITM Web of Conferences · 2025
This work focuses on implementation/designing the RISC-V Processor with optimized pipeline throughput, cache hit rate, and dynamic instruction scheduling to enhance the processing speed and energy efficiency. RISC-V extension used to support the tasks in AI, signal processing and cryptography. Design of processor will be implemented by using Verilog/VHDL and simulation tools later it will be tested on FPGA hardware. This project in designing to improve the performance mainly used for high-performance application.
Cited by 1Open access
Tak Wong, Stan Jarzabek, Soe Myat Swe et al. · 2001
A quantitative study has shown that frame technology [1] supported by Fusion toolset can lead to reduction in time- tomarket (70%) and project costs (84%). Frame technology has been developed to handle large COBOL- based business software product families. We wished to investigate how the principle of frame approach can be applied to support product families in other application domains, in particular to build distributed component- based systems written in Object- Oriented languages. As Fusion is tightly coupled with COBOL, we implemented our own tools based on frame concepts using the XML technology. In our solution, a generic architecture for a product family is a hierarchy of XML documents. Each such document contains a reusable program fragment instrumented for change with XML tags. We use a tool built on top of XML parsing framework JAXP to process documents in order to produce a custom member of a product family. Our solution is cost- effective and extensible. In the paper, we describe our solution, illustrating its use with examples. We intend to make our solution available to public in order to encourage investigation of frame concepts in other application domains, implementation languages and platforms.
Cited by 25
Tak Wong, Stan Jarzabek, Soe Myat Swe et al. · ACM SIGSOFT Software Engineering Notes · 2001
A quantitative study has shown that frame technology [1] supported by Fusion toolset can lead to reduction in time- tomarket (70%) and project costs (84%). Frame technology has been developed to handle large COBOL- based business software product families. We wished to investigate how the principle of frame approach can be applied to support product families in other application domains, in particular to build distributed component- based systems written in Object- Oriented languages. As Fusion is tightly coupled with COBOL, we implemented our own tools based on frame concepts using the XML technology. In our solution, a generic architecture for a product family is a hierarchy of XML documents. Each such document contains a reusable program fragment instrumented for change with XML tags. We use a tool built on top of XML parsing framework JAXP to process documents in order to produce a custom member of a product family. Our solution is cost- effective and extensible. In the paper, we describe our solution, illustrating its use with examples. We intend to make our solution available to public in order to encourage investigation of frame concepts in other application domains, implementation languages and platforms.
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Antonio González, Fernando Latorre, Grigorios Magklis · Synthesis lectures on computer architecture · 2010
Cited by 46Open access
2013
Execution) project, was formed to investigate high performance computer architectures that would be well suited to VLSI implementation. One of the primary goals of the project was to devise architectural methods of minimizing the impact of off-chip memory accesses on processor
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P. Saiprathyusha, C. Chandrasekhar · Springer Link (Chiba Institute of Technology) · 2025
This work focuses on implementation/designing the RISC-V Processor with optimized pipeline throughput, cache hit rate, and dynamic instruction scheduling to enhance the processing speed and energy efficiency. RISC-V extension used to support the tasks in AI, signal processing and cryptography. Design of processor will be implemented by using Verilog/VHDL and simulation tools later it will be tested on FPGA hardware. This project in designing to improve the performance mainly used for high-performance application.
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Viljainen, Martti · Aaltodoc (Aalto University) · 2020
Digitaalinen media on kaiken aikaa vienyt asemia analogiselta. \nNykyään myös audiota käsitellään paljolti digitaalisessa muodossa. \nSignaaliprosessorit ovat mahdollistaneet monimutkaisten algoritmien reaaliaikaisen suorittamisen, mitä tarvitaan mm. audiokompressoinnissa. \nHaasteita audion tehokkaaseen koodaukseen ovat tuoneet Internetin ja langattomien järjestelmien multimediasovellukset, jotka vaativat pientä siirtokaistaa ja talletuskapasiteettia. \n\nTässä työssä esitellään MPEG-l layer 2 -algoritmi sekä sen toteutus TMS320VC5402signaaliprosessorilla. \nMenetelmää tarvitaan laajakaistaisen audion tehokkaaseen siirtämiseen IP-verkon yli. \nVastaanottopäässä lähetetty signaali saadaan rekonstruoitua purkamalla kompressio. \nToteutuksen lisäksi työssä esitellään yleisesti audiokoodaukseen liittyviä periaatteita. \nPääpaino on perkeptuaalisissa menetelmissä, jotka perustuvat kuulon psykoakustisiin ominaisuuksiin.
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Zdravko Todorov, Danijela Efnusheva, Ана Чолакоска et al. · SHILAP Revista de lepidopterología · 2021
With the increasing number of Internet devices, the emergence of IoT, 5G and the increased traffic between the devices, the IPv6 is complementing IPv4. As IPv6 is becoming the protocol of choice by the new technologies, in order to accommodate for the features demanded by these technologies it is necessary to have high speed and low latency between the connected nodes. This paper introduces a hardwired IPv6 FPGA node, which processes IPv6 packets and is focused on high-speed transmission. Although, the code is written VHDL, it is written in a way which enables the user to easily add new features and implement new extension headers. The implementation of this IPv6 header processor is one on a Virtex7 VC709 FPGA development board.
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A. J. Fisher · Software Practice and Experience · 1986
Abstract This paper describes an implementation of the concurrent programming language occam on a multi‐processor computer, in which occam channels are multiplexed onto a token ring which links the processors.
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B.J. Schacter, J.E. Brewer · 2003
Advantages exist for implementation of neural networks using emerging monolithic processor devices that incorporate communication resources and large amounts of memory. The MSPSE (monolithic synchronous processor slave element) device currently under development is representative of a broad class of emerging devices with both computation and communication capability. The MSPSE's high computing throughput, large internal memory, and ability to operate multiple instruction multiple data (MIMD) or single instruction/multiple data (SIMD) mode make it suitable for implementation of neural networks.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Jorge Eliécer Duque Pardo · Universidad Industrial de Santander · 2006
Este trabajo de investigación comprende el diseño y construcción de un procesador de comunicaciones que utiliza el protocolo Modbus para comunicación con diferentes dispositivos de control de procesos o instrumentación tales como PLCs, medidores de energía, transmisores y actuadores. Se utilizó un microcontrolador HCS12 de Motorola para la implementación del protocolo Modbus y para la realización de las operaciones de adquisición, conversión analógica Œdigital y comunicación serial. Las características funcionales establecidas para el Procesador de Comunicación fueron: - Capacidad de manejo de las interfaces RS-232 y RS-485 - Posibilidad de trabajar en cualquiera de los modos de transmisión Modbus ASCII o RTU. - Implementación de 15 funciones Modbus para el acceso y manipulación de datos, tanto a nivel de bits como a nivel de registros de 16 bits, y funciones de diagnóstico y configuración. - Capacidad para manejar hasta 2024 bits y 250 registros de 16 bits. - Posibilidad de implementar aplicaciones en el sistema embebido, aparte de las funciones específicas de comunicación. - Portabilidad del firmware para la implementación en otros sistemas embebidos. - Posibilidad de configuración por hardware o software de los parámetros de comunicación: rata de baudios, paridad y tipo de interfaz. La arquitectura abierta del protocolo Modbus permitió su implementación en diferentes plataformas de software y de hardware. Esto se comprobó al implementar el procesador Modbus esclavo en un microcontrolador de 16 bits y el maestro en un PC utilizando el software LabView. También se pudo comprobar la interoperabilidad con diferentes fabricantes de software y hardware Modbus, al conectar el procesador Modbus a una red industrial RS-485.
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Daniel Lewin, et al. · 2007
We address the problem of verification of implementations of complex processors using architectural level automatic test program generators. A number of automatic test program generators exist, and are widely used for verification of the compliance of complex processors with their architectures. We define a four stage verification process: (1) describing the processor implementation control as a Finite State Machine (2) deriving transition coverage on the FSM using methods from formal verification (3) translation of the covering tours to constraints on test programs (4) generation of test programs for each set of constraints. This process combines a high quality and well defined theoretical method along with tools used in industrial practice. There are a
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Pravin Mane, Indra Gupta, M.K. Vasantha · 2006
A true 16-bit RISC processor has been designed using VHDL. Hierarchical approach has been used so that basic units can be modeled using behavioral programming. These basic units are combined using structural programming. Four stage (viz. instruction fetch stage, instruction decode stage, execution stage and memory/IO-writeback stage) pipelining is used to improve the overall CPI (clock cycles per instruction). Hardwired control approach is used to design the control unit as against microprogrammed control approach in conventional CISC processor. The processor has one input port, one output port and six hardware vectored interrupts along with 16-bit address bus and 16-bit data bus. Structural hazards are dealt with the implementation of prefetch unit, data hazards are dealt with forwarding and control hazards are dealt with flushing and stalling. The design has been implemented on FPGA for verification purpose.
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E. P. Vasilakopoulou, George Papadopoulos, George E. Karastergios · Wireless Communications and Mobile Computing · 2003
Abstract In recent years, wireless access networks offer an alternative method for connecting subscribers to the global communication network. Several high‐speed Wireless LAN's (WLAN) standards have emerged and among them the ETSI BRAN HiperLAN II standard is distinguished for its performance and QoS support. This paper, starting with a short overview of HiperLAN II main features and Medium Access (MAC) protocol, presents the architecture of an implemented high‐speed Frame Processor that realizes the medium access control (MAC) protocol of the HiperLAN II standard. The main goal of the Frame Processor is the real‐time management of the air interface as well as to bridge the upper network layers with the wireless world, relieving the data link control (DLC) layer of time‐consuming tasks such as slot map allocation extraction, bit‐by‐bit processing of data units, framing and synchronization. Copyright © 2003 John Wiley & Sons, Ltd.
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