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article · 2010

Structured ASIC: Methodology and comparison

Sam M. H. Ho, Steve C. L. Yuen, Hiu Ching Poon, Thomas Chau, Yanqing Ai, Philip H. W. Leong, Oliver C. S. Choy, Kong‐Pang Pun

Cited by 4Abstract and details only

Abstract

As fabrication process technology continues to advance, mask set costs have become prohibitively expensive. Structured ASICs can offer price and performance between ASICs and FPGAs. They are attractive for mid-volume production and offer good intellectual property security. In this paper, a structured ASIC methodology, where 2 metal- and 1 via-mask are customised, is described. The CAD tools are fully compatible with conventional ASIC design flows and a comparison of area and delay performance with ASICs and FPGAs is given. A prototype structured ASIC implementing an LED-backlit LCD controller was fabricated in a 0.13 μm CMOS process. It was verified and power consumption compared with an ASIC design.

Cite this paper

APA 7

Ho, S. M. H., Yuen, S. C. L., Poon, H. C., Chau, T., Ai, Y., Leong, P. H. W., Choy, O. C. S., & Pun, K. (2010). Structured ASIC: Methodology and comparison. https://doi.org/10.1109/fpt.2010.5681422

MLA 9

Ho, Sam M. H., et al. “Structured ASIC: Methodology and comparison.” 2010, pp. 377–80, https://doi.org/10.1109/fpt.2010.5681422.

Chicago

Ho, Sam M. H., Steve C. L. Yuen, Hiu Ching Poon, Thomas Chau, Yanqing Ai, Philip H. W. Leong, Oliver C. S. Choy, and Kong‐Pang Pun. 2010. “Structured ASIC: Methodology and comparison.” https://doi.org/10.1109/fpt.2010.5681422.

Harvard

Ho, S.M.H. et al. (2010) ‘Structured ASIC: Methodology and comparison’. Available at: https://doi.org/10.1109/fpt.2010.5681422.

BibTeX
@article{ho2010structured,
  title = {{Structured ASIC: Methodology and comparison}},
  author = {Ho, Sam M. H. and Yuen, Steve C. L. and Poon, Hiu Ching and Chau, Thomas and Ai, Yanqing and Leong, Philip H. W. and Choy, Oliver C. S. and Pun, Kong‐Pang},
  pages = {377--380},
  year = {2010},
  doi = {10.1109/fpt.2010.5681422}
}

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