article · 2013

120 V super junction LDMOS transistor

Sumit Kumar Panigrahi, Usha Gogineni, Maryam Shojaei Baghini, Farshid Iravani

Cited by 7Abstract and details only

Abstract

Super junction (SJ) is one of the emerging principles used in high-voltage high-power semiconductor devices. Implementation of SJ principle with charge balance in the pillars has overcome the “Silicon-limit”. SJ principle demands formation of back-to-back reverse biased p-n pillars. Main technology constraint is formation of narrow pillars with high aspect ratio and charge imbalance in these pillars. We propose a method to obtain high breakdown voltage in planar SJ-LDMOS by reducing the effect of charge imbalance at the drain end without reducing width of the pillars and no significant change in I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> . The breakdown voltage of 120 V in a HV CMOS technology with tox of 13nm is achieved without ION degradation, as compared to 100 V conventional LDMOS device.

Cite this paper

APA 7

Panigrahi, S. K., Gogineni, U., Baghini, M. S., & Iravani, F. (2013). 120 V super junction LDMOS transistor. https://doi.org/10.1109/edssc.2013.6628135

MLA 9

Panigrahi, Sumit Kumar, et al. “120 V super junction LDMOS transistor.” vol. 19, 2013, pp. 1–2, https://doi.org/10.1109/edssc.2013.6628135.

Chicago

Panigrahi, Sumit Kumar, Usha Gogineni, Maryam Shojaei Baghini, and Farshid Iravani. 2013. “120 V super junction LDMOS transistor.” https://doi.org/10.1109/edssc.2013.6628135.

Harvard

Panigrahi, S.K. et al. (2013) ‘120 V super junction LDMOS transistor’. Available at: https://doi.org/10.1109/edssc.2013.6628135.

BibTeX

@article{panigrahi2013super,
  title = {{120 V super junction LDMOS transistor}},
  author = {Panigrahi, Sumit Kumar and Gogineni, Usha and Baghini, Maryam Shojaei and Iravani, Farshid},
  volume = {19},
  pages = {1--2},
  year = {2013},
  doi = {10.1109/edssc.2013.6628135}
}

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