Lai, Sz-Hau, Fager, Christian, Kuylenstierna, Dan et al. · Chalmers Publication Library (Chalmers University of Technology) · 2013
This article describes the detailed efforts of the winning contribution of the first student competition in microwave transistor modeling, held at the 2012 International Microwave Symposium (IMS2012) in Montreal, Quebec, Canada. The competition was sponsored by MTT-1, Freescale Semiconductor Inc., and WIN Semiconductor Inc. The transistor modeled was a commercially available high-power device from Freescale, and the characterization data required for modeling was distributed to all competitors. No measurements were to be carried out by the participants, so all students world wide, even those without expensive transistor characterization equipment, could participate. The main objectives of the competition were to identify the technology and develop a nonlinear model from the provided measurement data set [e.g., cold field effect transistor (FET) measurements, pulsed IV, IV versus temperature, S parameter versus bias, and pulsed S-parameter measurements] . The developed model was also to be validated versus large signal one-and two-tone measurements. The validation data was in the form of output power and power added efficiency (PAE) versus input power and measured at two different conditions, e.g., input/output terminations for maximum efficiency and maximum output power, respectively. An accurate model should be able to predict the large signal measurements across the full range of input power levels and bias points available. The judgment of the modeling result was based on the agreement between model simulation and measurement in terms of output power, efficiency, and third-order intermodulation (IM3) versus input power, several of which were not provided to the competitors. © 2000-2012 IEEE.
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Moilanen, Pekka · Theseus (Ammattikorkeakoulujen) · 2018
Kaksi suurta tehotransistorivalmistajaa yhdistivät komponenttien valmistus-, testaus- ja kokoon-panolinjoja. Tämän johdosta täytyi uuden tyypin LDMOS-transistori testata Nokian tukiasema-tuotteissa.\n\nTyön toimeksiantaja oli Nokia Solutions and Networks, jonka mobiilitukiasematuotteissa kompo-nentti on laajalti käytössä.\n\nTyön tavoitteena oli tehovahvistinmoduulin (PA-moduuli) ja lähetin-vastaanotinyksikölle tehtyjen RF-laboratoriotestien perusteella ja vertaamalla suorituskykyä nykyiseen tuotteeseen tutkia, onko uuden tyypin komponentti soveltuva massatuotantoon.\n\nTestituloksien perusteella tehtiin päätös uuden komponenttityypin käyttöönotosta.
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Melick, NGH Nico van · TU/e Research Portal (Eindhoven University of Technology) · 1996
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Loginov, Dmitrii · Brno University of Technology Digital Library (Brno University of Technology) · 2019
V této bakalářské práci je provedeno porovnání struktury LDMOS oproti konvenční MOS struktuře. Anomální efekty, výzvy, které tato struktura přináší do oblasti modelování a charakterizace jsou popsány v první kapitole. Další část této práce se zaměřuje na existující možné přístupy v charakterizaci LDMOS struktury, které se používají v polovodičovém průmyslu. V druhé kapitole je také popsána BSIM metodologie, která je dále použitá pro vytváření modelu LDMOS popisujícího DC a CV chování. Kroky charakterizace, která probíhala v laboratoři ON Semiconductor, jakožto měření součástky a ladění charakteristik modelu až do výsledného souboru parametrů BSIM4, jsou uvedeny v posledních kapitolách této práce.
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Shuming Xu, K.P. Gan, Ganesh S. Samudra et al. · IEEE Transactions on Electron Devices · 2000
A new device structure named IDLDMOS is proposed to overcome the power LDMOS limit (R/sub on, sp/ /spl prop/ BV/sub dss//sup 2.5/). The concept is based on replacing LDMOS lightly doped n-drift region by moderately doped alternating p and n layers of suitable dimension and doping. Off state requirement is achieved by mutual lateral-depletion of the alternating layers. Using small identical lateral width for both p and n layers, a doping concentration of up to two orders of magnitude higher than n-drift concentration in a conventional case can he achieved to reduce the on-resistance R/sub on/. The simulated 120 V IDLDMOS on SOI substrate has shown a R/sub on/ value that is about 38% of the corresponding R/sub on/ value of a conventional n/sup -/ LDD type LDMOS. At a R/sub on, sp/ value of 1.15 m/spl Omega/-cm/sup 2/ with BV/sub dss/ of 124 V, IDLDMOS has exceeded the conventional LDMOS limit. Compared to conventional LDMOS, IDLDMOS is less prone to quasisaturation at high gate and drain voltage due to its higher drain doping. Isothermal simulation has shown that there was no deterioration in both AC and transient performance between the two devices. Nevertheless, the lower V/sub d, sat/ of LDLDMOS is expected to yield a higher g/sub m/ at the same level of current conduction as in the conventional structure.
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Rare & Special e-Zone (The Hong Kong University of Science and Technology) · 2000
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Р. Алексеев, И. Семейкин, А. Цоцорин et al. · ELECTRONICS Science Technology Business · 2023
Приводятся сведения об усовершенствованиях технологии LDMOS в АО «НИИЭТ», а также о разрабатываемых предприятием СВЧ-транзисторах, основанных на данной технологии и предназначенных для применения в телевизионной аппаратуре стандартов DVB-T / DVB-T2.
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T. Paul Chow, B. Jayant Baliga · IEEE Transactions on Electron Devices · 1988
A hybrid VIGBT-LDMOS transistor which consists of a VIGBT (vertical insulated-gate bipolar transistor) path with a lateral DMOSFET path, implemented in a 300-V, p-channel version, has been demonstrated. The device can be operated with series resistors attached to either the collector or the drain terminals. The case in which the collector resistor equals zero is called the LACOSH-VIGBT (lateral collector shorted-vertical IGBT), and the case in which the drain resistor equals zero is called LABIENFET (lateral bipolar enhanced DMOSFET). Experimental characterization of the LACOS-VIGBT showed that the onset of the minority injection is retarded from 0.6 to 1.1 V, and the forward drop varies from 1.4 to 3.6 V and from 1.1 to 3.0 V, with and without the collector short, respectively, for 1 A (14 A/cm/sup 2/) to 6 A (83 A/cm/sup 2/) of collector current. Corresponding improvements in turnoff times are 5.5-4.4 mu s vs. 9.5-7.2 mu s. The reverse conducting diode has a forward drop of 0.82-1.57 V for 1-6 A of current and a switching time over 10 mu s. In the LABIENFET mode, the forward drop at 1 A (14 A/cm/sup 2/) decreases from 15.6 to 1.4 V when the collector series resistance changes from 150 to 0 Omega , with corresponding turnoff times of 1.7-5.5 mu s. This device is attractive either as a fast switching VIGBT or as a low-voltage-drop FET, with an integral antiparallel diode.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Loginov, Dmitrii · Brno University of Technology Digital Library (Brno University of Technology) · 2019
V této bakalářské práci je provedeno porovnání struktury LDMOS oproti konvenční MOS struktuře. Anomální efekty, výzvy, které tato struktura přináší do oblasti modelování a charakterizace jsou popsány v první kapitole. Další část této práce se zaměřuje na existující možné přístupy v charakterizaci LDMOS struktury, které se používají v polovodičovém průmyslu. V druhé kapitole je také popsána BSIM metodologie, která je dále použitá pro vytváření modelu LDMOS popisujícího DC a CV chování. Kroky charakterizace, která probíhala v laboratoři ON Semiconductor, jakožto měření součástky a ladění charakteristik modelu až do výsledného souboru parametrů BSIM4, jsou uvedeny v posledních kapitolách této práce.
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Mashad Nemati, Hossein, Grahn, Jan, Fager, Christian · Chalmers Publication Library (Chalmers University of Technology) · 2010
A band-reconfigurable LDMOS high power amplifier (PA) with state-of-the-art performance is presented. The frequency reconfigurability is implemented by band-switchable matching networks using PIN diodes. The PA provides power-added efficiencies which are higher than 61% and output power levels exceeding 8 W at 0.9 GHz, 1.5 GHz, and 1.9 GHz. The input return loss in all the three bands is better than 12 dB.
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Kunnari, Matti · Aaltodoc (Aalto University) · 2002
Tässä diplomityössä käsitellään ja tutkitaan LDMOS-transistoriteknologian soveltuvuutta WCDMA-järjestelmän tukiaseman tehovahvistinsovelluksiin. Diplomityön ensimmäinen osa käsittelee yleistä tehovahvistimen teoriaa ja erityisiä WCDMA-järjestelmän vaatimuksia tehovahvistimelta. Lisäksi esitetään suunnittelun lähtökohtana oleva load-pull -menetelmä sekä LDMOS-transistoriteknologia ja sen ominaisuudet. Toisessa osassa LDMOS-teknologian toimivuus ja sopivuus WCDMA-järjestelmän tukiaseman tehovahvistimeksi todennetaan suunnittelemalla AB-luokassa toimiva mahdollisimman lineaarinen ja hyötysuhteeltaan hyvä tehovahvistin käyttäen LDMOS-transistorin suursignaalimallia tietokonesimuloinneissa. Käytännön mittauksin varmistetaan vahvistimen toiminta vertaamalla mitattuja tuloksia suursignaalimallin antamiin simulointituloksiin sekä 3GPP:n määrittämiin vaatimuksiin. LDMOS-transistoriteknologia ja sen suursignaalimalli osoittautuivat soveliaiksi WCDMA-järjestelmän tukiaseman tehovahvististinsovelluksiin, ja suunnitellun tehovahvistimen parannetun version mitattu suorituskyky ylitti tyypilliset suorituskykyarvot, jotka transistorivalmistajat tuotteilleen lupaavat. Toisen version parannetun vahvistimen suorituskykyarvot ovat: P_(out) = 30 W, Gp = 13.5 dB, ACP = -45 dBc, kun P_(out, ave) = 4.4 W ja PAE = 17.5%.
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E.C. Griffith, Seán Kelly, J.A. Power et al. · 2000
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Seung‐Chul Lee, Jae-Keun Oh, Min‐Koo Han et al. · Physica Scripta · 2002
A new vertical channel LDMOS, which decreases the on-resistance without sacrificing the breakdown voltage, is proposed and verified by numerical simulation. In the proposed vertical channel LDMOS, the channel and the drift region are located in the trench between the source and the drain. The total cell pitch of the proposed device is decreased to 4 μm which is about a half of the conventional LDMOS when the breakdown voltage is 60 V. Simulation results show that the on-resistance is 0.45 mΩ · cm2 for a 60 V breakdown voltage which is very low compared to that of the conventional LDMOS.
Cited by 1
Zhihui Yu, Hao Jin, Shurong Dong et al. · Microelectronics Reliability · 2015
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Il-Yong Park, C. T. Salama · IEEE Circuits and Devices Magazine · 2006
The super junction (SJ) concept (Coe et al.) applied to power semiconductor devices is attractive due to its potential for reducing on-resistance at a given breakdown voltage. Discrete SJ vertical power devices have recently become available commercially. However, lateral SJ devices have not materialized for several years partly due to the fact that the lateral SJ structure, implemented on silicon substrates, suffers from substrate-assisted depletion effects which reduce the breakdown voltage. This article discusses the various device structures that have been proposed to eliminate the substrate-assisted depletion effects in SJ-lateral double diffused MOS LDMOS transistors (SJ-LDMOSTs). The concept of the SJ device and vertical and lateral SJ structure was summarized. The substrate-assisted depletion effects are described in detail. The alternative implementations proposed to suppress the substrate effects were then discussed. And the experimental implementation results are summarized and discussed to identify the most likely option for the implementation of lateral SJ-LDMOSTs
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Sumit Kumar Panigrahi, Usha Gogineni, Maryam Shojaei Baghini et al. · 2013
Super junction (SJ) is one of the emerging principles used in high-voltage high-power semiconductor devices. Implementation of SJ principle with charge balance in the pillars has overcome the “Silicon-limit”. SJ principle demands formation of back-to-back reverse biased p-n pillars. Main technology constraint is formation of narrow pillars with high aspect ratio and charge imbalance in these pillars. We propose a method to obtain high breakdown voltage in planar SJ-LDMOS by reducing the effect of charge imbalance at the drain end without reducing width of the pillars and no significant change in I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> . The breakdown voltage of 120 V in a HV CMOS technology with tox of 13nm is achieved without ION degradation, as compared to 100 V conventional LDMOS device.
Cited by 7
Ldmos Power, Modules Two · 2014
Providing both amateurs and professionals with the tools needed to create their own “twoway radio.” Abstract: Two-way radios are today present in almost every area of our public life. They are an invaluable tool supporting professionals in a wide range of industries ranging from transportation to energy, government and others. With two-way radios, there’s no need to deploy supporting infrastructure in the field. In fact, two-way radios can offer an instant communication (private and cost-effective) anywhere and anytime. Nevertheless, there is a vast and growing market among non-professional users who demand high-quality yet affordable equipment. The purpose of this article is to provide both amateurs and professionals with the tools needed to create their own “ two-way radio ” not linked to any specific standard product present in the market. This allows greater integration in radio systems currently in development, and in general, a considerable saving on production costs.
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Peng Zhang, Yuan Wang, Song Jia et al. · Semiconductor Science and Technology · 2012
A study of LDMOS–SCR devices for SOI BCD technology is presented. The LDMOS–SCR is fully compatible with BCD process and can replace the LDMOS as a high voltage output driver. By comparison of the LDMOS and another 'pnpn' type of LDMOS–SCR, the triggering mechanism and ESD behavior are well discussed with both device simulation and TLP measurement. It is verified that the ESD performance of the LDMOS–SCR is much improved compared with the LDMOS.
Cited by 9
Juan A. Herbsommer, H. Safar, W. C. Brown et al. · 2002
We present the electrical and thermal performance of ultra-thin RF LDMOS devices. Following a proprietary process, we fabricated such devices with a thickness as reduced as 40μm. This results in a reduction of the operating junction temperature, as demonstrated by infrared imaging experiments and three-dimensional finite-element-analysis simulations. As a result, the thermal resistance of our packaged devices reaches substantially lower values than industry standard. This allows for a higher power output and improved efficiency, as demonstrated by RF measurements.
Cited by 5
J. Lin P. Hower · 2005
This paper presents a new method of enhancing the SOA of n-channel Ldmos transistors. Attention is focused on those applications where “Electrical SOA” is important and where the power pulse time is typically a few µs or less. Typical applications include gate drives, H-bridge commutation, and self-protection against ESD pulses.
Cited by 72