article · IEEE Electron Device Letters · 2000
IC test structures for multilayer interconnect stress determination
S. Smee, Michael Gaitan, Donald B. Novotny, Yogendra Joshi, D.L. Blackburn
Cited by 16Abstract and details only
Abstract
A new method for measuring strain in multilayer integrated circuit (IC) interconnects is presented. This method utilizes process compatible MEMS-based test structures and is applied to the determination of longitudinal interconnect stress in a standard dual-metal-layer CMOS process. Strain measurements are shown to be consistent for an array of similar test structures. Stress values, calculated from constitutive relations, are in good agreement with published results.
Cite this paper
Smee, S., Gaitan, M., Novotny, D. B., Joshi, Y., & Blackburn, D. (2000). IC test structures for multilayer interconnect stress determination. IEEE Electron Device Letters, 21(1), 12–14. https://doi.org/10.1109/55.817437
Smee, S., et al. “IC test structures for multilayer interconnect stress determination.” IEEE Electron Device Letters, vol. 21, no. 1, 2000, pp. 12–14, https://doi.org/10.1109/55.817437.
Smee, S., Michael Gaitan, Donald B. Novotny, Yogendra Joshi, and D.L. Blackburn. 2000. “IC test structures for multilayer interconnect stress determination.” IEEE Electron Device Letters 21 (1): 12–14. https://doi.org/10.1109/55.817437.
Smee, S. et al. (2000) ‘IC test structures for multilayer interconnect stress determination’, IEEE Electron Device Letters, 21(1), pp. 12–14. Available at: https://doi.org/10.1109/55.817437.
@article{smee2000test,
title = {{IC test structures for multilayer interconnect stress determination}},
author = {Smee, S. and Gaitan, Michael and Novotny, Donald B. and Joshi, Yogendra and Blackburn, D.L.},
journal = {IEEE Electron Device Letters},
volume = {21},
number = {1},
pages = {12--14},
year = {2000},
doi = {10.1109/55.817437}
}Made from the index record. Check names, capitalisation and page numbers against the paper. Need another style? AI for Research has over 10,000.