Skip to content
Free planNo credit card requiredStart writing

article · IEEE Journal of Solid-State Circuits · 1984

A subnanosecond 8K-gate CMOS/SOS gate array

S. Tanaka, Jun Iwamura, J. Ohno, K. Maeguchi, H. Tango, K. Doi

Cited by 16Abstract and details only

Abstract

An 8370-gate CMOS/SOS gate array has been developed using a Si-gate CMOS/SOS process with two-level metallization. The gate lengths of the transistors are 1.8 and 1.9 /spl mu/m for the n-channel and p-channel, respectively. Subnanosecond typical gate delay times have been obtained. Typical delay times of inverter, two-input NAND, and two-input NOR gates are 0.67, 0.87, and 0.99 ns, respectively, under a typical loading condition (three fan outs and 2 mm first metal). It is shown that ECL speed with CMOS power can be achieved in a system by using the CMOS/SOS gate array. Advantages of the SOS device on speed performance are also discussed.

Cite this paper

APA 7

Tanaka, S., Iwamura, J., Ohno, J., Maeguchi, K., Tango, H., & Doi, K. (1984). A subnanosecond 8K-gate CMOS/SOS gate array. IEEE Journal of Solid-State Circuits, 19(5), 657–663. https://doi.org/10.1109/jssc.1984.1052205

MLA 9

Tanaka, S., et al. “A subnanosecond 8K-gate CMOS/SOS gate array.” IEEE Journal of Solid-State Circuits, vol. 19, no. 5, 1984, pp. 657–63, https://doi.org/10.1109/jssc.1984.1052205.

Chicago

Tanaka, S., Jun Iwamura, J. Ohno, K. Maeguchi, H. Tango, and K. Doi. 1984. “A subnanosecond 8K-gate CMOS/SOS gate array.” IEEE Journal of Solid-State Circuits 19 (5): 657–63. https://doi.org/10.1109/jssc.1984.1052205.

Harvard

Tanaka, S. et al. (1984) ‘A subnanosecond 8K-gate CMOS/SOS gate array’, IEEE Journal of Solid-State Circuits, 19(5), pp. 657–663. Available at: https://doi.org/10.1109/jssc.1984.1052205.

BibTeX
@article{tanaka1984subnanosecond,
  title = {{A subnanosecond 8K-gate CMOS/SOS gate array}},
  author = {Tanaka, S. and Iwamura, Jun and Ohno, J. and Maeguchi, K. and Tango, H. and Doi, K.},
  journal = {IEEE Journal of Solid-State Circuits},
  volume = {19},
  number = {5},
  pages = {657--663},
  year = {1984},
  doi = {10.1109/jssc.1984.1052205}
}

Made from the index record. Check names, capitalisation and page numbers against the paper. Need another style? AI for Research has over 10,000.

A modeling technique for CMOS gates

Alexander Chatzigeorgiou, S. Nikolaidis, Ioannis A. Tsoukalas · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1999

Cited by 71