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article · 2002

Exploiting instruction level parallelism with the DS architecture

Yinong Zhang, G Adam

Cited by 5Abstract and details only

Abstract

A new architecture, DS, for exploiting instruction level parallelism is proposed in this paper. DS splits the program into two instruction substreams with the dominant one navigating the control flow and the subsidiary one carrying out the rest of the computational task. Compiler techniques associated with the DS architecture are discussed, with the goal of minimizing communication and balancing computation. Performance is compared with an aggressive 8-way superscalar processor. In general, DS can deliver the same IPC as the superscalar. This is achieved with less complex hardware and better potential for fast clock rates.

Cite this paper

APA 7

Zhang, Y., & Adam, G. (2002). Exploiting instruction level parallelism with the DS architecture. https://doi.org/10.1109/icpp.1996.539060

MLA 9

Zhang, Yinong, and G Adam. “Exploiting instruction level parallelism with the DS architecture.” vol. 1, 2002, pp. 230–37, https://doi.org/10.1109/icpp.1996.539060.

Chicago

Zhang, Yinong, and G Adam. 2002. “Exploiting instruction level parallelism with the DS architecture.” https://doi.org/10.1109/icpp.1996.539060.

Harvard

Zhang, Y. and Adam, G. (2002) ‘Exploiting instruction level parallelism with the DS architecture’. Available at: https://doi.org/10.1109/icpp.1996.539060.

BibTeX
@article{zhang2002exploiting,
  title = {{Exploiting instruction level parallelism with the DS architecture}},
  author = {Zhang, Yinong and Adam, G},
  volume = {1},
  pages = {230--237},
  year = {2002},
  doi = {10.1109/icpp.1996.539060}
}

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