Skip to content
Free planNo credit card requiredStart writing
AI for Research home
AI for Research home
Dashboard
Sign inGet started

Search 250 million research papers

Read the abstract, see who wrote it and who cites it, and get the citation in APA, MLA, Chicago or Harvard.

About 10,000 papers for “Gate array”

500 Gates GaAs Gate Array

Nobuyuki Toyoda, Toshiyuki Terada, M. Mochizuki et al. · Japanese Journal of Applied Physics · 1983

High speed GaAs DCFL gate array consisting of 500 3-INPUT NOR gates, in which 2000 FETs are integrated, has been successfully fabricated by a Pt buried gate planar E/D process technology. Eleven different 15-stage ring oscillators were made on this gate array to investigate the dependence of gate performance on various loading conditions. Typical propagation delay times per gate were 0.16 ns and 0.69 ns under unloaded and loaded (fan-out=3, interconnection length=3 mm, cross-over=20) conditions at a power dissipation of 0.50 mW for 1.7 µm gate devices.

Cited by 2

Field-Programmable Gate Array Architectures

Steven J. E. Wilton, Nathalie Chan King Choy, Scott Y. L. Chin et al. · Auerbach Publications eBooks · 2008

This chapter discusses the stage by describing the architecture of Field-programmable gate arrays (FPGAs). It describes several programming technologies. The chapter also describes logic block architectures. It examines routing architecture and also discusses embedded memories and embedded computation blocks. The tracks are connected to each other and to the logic blocks using programmable switches. Commercial FPGAs often contain combined switch blocks and connection blocks, however for clarity, this section will describe each separately. Therefore, Flash-based FPGAs have a slower time-to-market compared to the static random access memory-based FPGAs. Distributed memory, on the other hand, uses small memories spread across the entire FPGA chip, often implemented in unused logic elements. To support applications involving microcontrollers and microprocessors, FPGA manufacturers offer embedded processors tailored to interface with the FPGA logic fabric. Switches in modern FPGAs are typically buffered, because unbuffered switches result in a quadratic increase in delay for long connections.

Cited by 0

Optically Programmable Gate Array (OPGA)

Jose M Mumbra, Demetri Psaltis, Gan Zhou et al. · Optics in Computing · 1999

Field Programmable Gate Arrays (FPGAs) are very versatile devices. A typical FPGA consists of an array of configurable logic blocks and a mesh of interconnections fully programmable by the user to perform a given application. By just changing its internal connectivity, the FPGAs can implement a totally different new function.

Cited by 2

Gate array selection advisor system

Chiu‐Sing Choy, C.H. Fung · 2002

An advisor system which is designed to assist a gate array novice to identify the appropriate parameters for selection and to rank the gate array products accordingly is presented. The system will rank the gate arrays, included in the knowledge files, in order of certainty factor based on the user's requirement, circuit specifications, and the vendor's capabilities. The system draws conclusions through interactive dialogue with the user. However, it also automatically generates necessary parameters from the circuit description itself. The inference process is constructed on an expert system development tool called S1. Universal standards are used as much as possible. Common practices and definitions are adopted in defining many parameters such as gate delay, gate size, etc. In order that the system can be expanded and fine-tuned, the knowledge base of product lines and many evaluation functions are external to the S1 core. The decision flow closely follows the practices of experienced gate array designers.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 1

Field Programmable Gate Array Designs

Lesley Shannon, Bibliographie Services, Bibliothèque Nationale et al. · 2014

reproduce, loan, distribute or sen copies of this thesis in microform, paper or electronic formats. The author retains ownership of the copyright in this thesis. Neither the thesis nor substantial extracts fiom it may be printed or otherwise reproduced without the author&amp;apos;s permission. L&amp;apos;auteur a accordé une licence non exclusive permettant à la Bibliothèque nationale du Canada de reproduire &amp;apos; prêter, distribuer ou vendre des copies de cette thèse sous la forme de microfiche/nlm, de reproduction sur papier ou sur format électronique. L&amp;apos;auteur conserve la propriété du droit d&amp;apos;auteur qui protège cette thèse. Ni la thèse ni des extraits substantiels de celle-ci ne doivent être imprimés ou autrement reproduits sans son autorisation. Impact of Intellectual Property Cores on

Cited by 0

Dynamic Optically Reconfigurable Gate Array

Minoru Watanabe, Fuminori Kobayashi · Japanese Journal of Applied Physics · 2006

Optically reconfigurable gate arrays (ORGAs) can readily enable both fast reconfiguration and numerous reconfiguration contexts using an optical holographic memory and optical wide-band reconfiguration connections. Such devices present the possibility of large virtual gate-count very large scale integrations (VLSIs). However, the real gate-count of the VLSI part of the devices is too small–only 80. Moreover, the reconfiguration speed is not sufficiently fast: 16 to 20 µs. For those reasons, this paper clarifies the architecture issues and presents a new architecture of a dynamic optically reconfigurable gate array (DORGA) to improve them. In addition, a comparison is made of results obtained using the previously proposed devices and DORGAs under the same environment. Finally, this paper presents a new design of a 51,272-gate-count DORGA with the new architecture.

Cited by 63

Optically differential reconfigurable gate array

Mototsugu Miyano, Minoru Watanabe, Fuminori Kobayashi · Electronics and Communications in Japan (Part II Electronics) · 2007

Abstract Recent years have seen the development of optically reconfigurable gate arrays, which can be reconfigured using light at high speeds that cannot be implemented with electrical wiring. However, optically reconfigurable gate arrays have reconfiguration speeds of 16 to 20 µs, which is fast compared to FPGAs (Field Programmable Gate Arrays), but high‐speed reconfiguration, approaching the operating clock of a mounted circuit, has not been implemented. Also, partial reconfiguration, which is indispensable for frequent dynamic reconfiguration, has not been considered. The authors propose an Optically Differential Reconfigurable Gate Array (ODRGA), which can be reconfigured at high speeds close to the operating clock of a mounted circuit and which allows partial reconfiguration of any zone in bit units. This paper includes an overview of ODRGA and introduces the optically differential reconfigurable architecture, with which arbitrary, partial reconfiguration is possible, as well as the optically reconfigurable architecture enabling high‐speed optical reconfiguration. Then, it is demonstrated that high‐speed optical reconfiguration at 200 ns, the world's fastest system‐level optical reconfiguration, is possible with an optical system using a pulse laser diode wherein nanosecond optical reconfiguration is possible with a prototype stand‐alone VLSI chip. Finally, it is made clear that, in the future, improvement to the optical components will make possible nanosecond high‐speed optical reconfiguration at the system level as well. © 2007 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 90(11): 132–139, 2007; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/ecjb.20420

Cited by 36

A sub nanosecond 8K-gate CMOS/SOS gate array

S. Tanaka, Jun Iwamura, J. Ohno et al. · 1984

A CMOS/SOS 8370-gate array has been developed using a 2μm Si-gate process. Typical propagation delay time for the 2-input NAND gate with a fan out of 3 and 2mm of metal interconnect loading is 0.87ns.

Cited by 3

A triple-level wired 24K-gate CMOS gate array

Taisuke Saigo, K. Niwa, Tatsuhiko Ohto et al. · IEEE Journal of Solid-State Circuits · 1985

A 24K-gate CMOS gate array has been developed using triple-level wiring and a hierarchical layout method. A typical delay time is 1.6 ns with a fanout of 3 and a 3-mm metal interconnect length. The master chip was designed to be freely divided into blocks. A previously developed digital signal processor has been realized on the array. The design time was reduced to 25% of the normal design cycle although the chip size is 3.3 times larger than was realized by a handcrafted design.

Cited by 10

A 10K-Gate CMOS Gate Array Based on a Gate Isolation Structure

K. Sakashita, Motoki Ueda, T. Arakawa et al. · IEEE Journal of Solid-State Circuits · 1985

This paper describes an effect of the "gate isolation" technique and its application to a 10K-gate CMOS gate-array VLSI chip. This gate array is fabricated using a 2-/spl mu/m n-well CMOS technology, with double-level metallization. As an example, a 32-bit parallel array multiplier is designed using a fully automatic CAD system. The density of CMOS gate arrays using gate isolation is estimated to be 1.10 to 1.26 times greater than that of the arrays using several types of oxide isolation, when implementing circuits with complexities on the order of 10K gates.

Cited by 7

GaAs heterojunction bipolar 1K gate array

Hen Yuan, W. V. McLevige, Hung Dah Shih et al. · 1984

This report will discuss the design, fabrication and performance of a 1K heterojunction I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> L gate array with a base bar size of 3.55 × 3.80mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , containing 1024 internal gates, 64 programmable I/O buffers and 8 pads for the power supply. For general circuit applications the layout provides 300 global wire channels: 150 each in the horizontal and vertical directions.

Cited by 10