Simon Tulloch · arXiv (Cornell University) · 2018
An experimental digital correlated double sampler (DCDS) video processor has been implemented in a Xilinx Artix FPGA. It uses an Opal Kelly XEM7010-A50 module that comes with an integrated USB2 interface for easy interfac-ing to a data acquisition PC. The FPGA has been coupled to a dual 16-bit 20Msps ADC and video preamplifiers. A synthetic CCD video waveform was provided by a high speed DAC also under FPGA control. VHDL-defined hardware implemented the differential averager algorithm which has been shown to give the optimal signal to noise ratio over a wide range of readout speeds. Hardware developed in this project is intended for eventual integration into a Xilinx Zynq-based system that combines the functionality of both a CCD controller and Linux-based data acquisition system.
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Hájek, Radek · Brno University of Technology Digital Library (Brno University of Technology) · 2016
Diplomová práce obsahuje teoretický základ, rozdělení a funkce procesorů. Shrnuje princip zřetězeného zpracování instrukcí a druhy hazardů v mikroarchitektuře procesorů. Dále seznamuje s možnostmi návrhu procesorů pomocí jazyku CodAL, který je vyvíjen firmou Codasip. V praktické části práce byl vytvořen model procesoru MicroBlaze od firmy Xilinx v jazyce CodAL. Navržený model byl otestován a implementován do obvodu FPGA v rámci praktické ukázky.
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Dasari Kamala Kumari · IOSR Journal of Electrical and Electronics Engineering · 2013
The implementation of 32 bit RISC processor with microprocessor without interlocked pipeline stages (MIPS) is presented. It was implemented in VHDL so as to reduce the instruction set present in the programmable memory. As the result the processor will contain the necessary logics for the implementation that requires fewer gates to be synthesized in the programmable matrix and has the capability to increase the speed of the target processor with reduced memory. In this paper we propose a novel technique of run-time loading of machine code for MIPS-32 soft-core processor. As we know, implementing fewer instructions on silicon reduces the complexity of the instruction decoder, the addressing logic, and the execution unit. This allows the machine to be clocked at a faster speed, since less work needs to be done each clock period. In this paper we used Xilinx-ISE tool for logical verification, and further synthesizing it on Xilinx-ISE tool using target technology and performing placing & routing operation for system verification.
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Sebastián López Suaréz, Jose Felix Algarín Cotes · 2024
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Iosr Journals, Popuri Venkateswarlu Dasari Kamala Kumari · Figshare · 2014
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Mikušek, Petr · Brno University of Technology Digital Library (Brno University of Technology)
Tato práce se zabývá studií architektur vhodných pro vestavěné procesory, mezi něž patří i přenosem spouštěné architektury (TTA). Tyto architektury se programují uvedením přenosů dat a operace se spouští jako jejich vedlejší efekt. V tradičních operací spouštěných architekturách (OTA) program přímo udává požadované operace. Přesuny dat jsou v režii hardware a nemohou být řízeny a optimalizovány kompilátorem v době kompilace. Tento přístup přináší spoustu výhod po stránkách hardwarových i softwarových. Cílem této práce bylo provést návrh a implementaci ukázkového TTA procesoru v jazyce VHDL s následným ověřením realizace v hradlovém poli FPGA. Tento procesor je navržen do značné míry jako generický, tj. nastavitelný sadou parametrů, jako je datová šířka, počty sběrnic, atd.
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Matthew Farrens, Andrew R. Pleszkun · 2002
PIPE (parallel instruction with pipelined execution) processor is a 32-bit pipelined single chip processor with a simplified load-store instruction set, a five stage pipeline, a two-cycle ALU, and the following unique features: architectural queues; delayed branch scheme; sophisticated instruction cache, branch register file; subroutine call support; and branch queues. The nMOS implementation and lessons learned from it are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Borivoje Furht, Peter Lee · IEEE Micro · 1984
This driver enables easy implementation of the Am9511 as a coprocessor in Intel 8085-based systems.
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Tai-Yuan Cheng, Edward T.-H. Chu, K. Leung · 1994
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Vladimir Petrović, Marko Ilić, Gunter Schoof et al. · 2011
The new spacecraft area network (SCAN) system for internal satellite communication provides the data transfer between different satellite components. The middleware (MW) switch processor is a main part of a new proposed approach. Instead of current board computer based systems, the new data transfer approach based on network provides more reliable solution. The processor is currently in fabrication process in the 250 nm IHP technology. This paper introduces the description of MW switch architecture, a comparison between possible architecture approaches and characteristics of the implemented MW Switch processor.
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S. Montenegro, G. Schoof, M. Ilic et al. · SHILAP Revista de lepidopterología · 2012
The new spacecraft area network (SCAN) system for internal satellite communication provides data transfer between different satellite components. The satellite components have their own communication protocols, which are translated by middleware (MW) switch processor into a universal middleware protocol, understandable for the satellite operating system. The MW switch processor is the main part of a new proposed approach. Instead of current board computer based systems, the new data transfer approach based on network provides a more reliable solution. The processor is fabricated in the 250 nm IHP technology. This paper introduces a description of MW switch architecture, a comparison between possible architecture approaches and the characteristics of the implemented MW Switch processor.
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Grant Hampson · 2002
This document describes a FPGA implementation and simulation of the FFT component of the IIP Radiometer RFI processor described in [1]. A possible implementation of this FFT component has been previously described in [2]. Here a single FFT processor will be implemented and tested before proceeding to a larger design consisting of many such
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Majid Pakdel · Maker Innovations Series · 2026
In Chapter 8, we explored communication interfaces and hardware interfacing techniques, demonstrating how FPGAs interact with peripherals using protocols like UART, SPI, and I2C. Now, in this chapter, we take a significant step forward by applying these foundational concepts to processor design, focusing on the implementation of a RISC-V architecture—an open source instruction set architecture (ISA) that has revolutionized modern computing.
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Brhel, Tomáš · Brno University of Technology Digital Library (Brno University of Technology) · 2018
In this thesis there is a design of universal time-variant convolution FIR processor. Proposed algorithm is ready to process long signals with reduced process delay. Furthermore, there are proposed methods for smooth crossfade between different impulse responses. Algorithm is implemented in Matlab environment and later as a VST plugin.
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Microprocessors and Microsystems · 1987
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Prathamesh Berde, Dr. R. D. Daruwala, Sachin Kharude · 2014
For any computing process we have to perform specific operations in sequence so as to operate and process the data in required sequence. The basic motto here is to design implement &amp; evaluate the reconfigurable processor. It is uses software hardware co-design environment. This reconfigurable processor works similarly like special purpose processors but at much lesser cost than in compared to them as the cost of the processor is important aspect in designing any system. The components are designed in VHDL in top level architecture. It is simulated and synthesized using Active HDL/Xilinx foundation series.
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S. Suresh, R. Ganesh · 2014
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Guru Satya Dattatreya Pandeeti, Janhvi Dixit, Asif Hussain et al. · 2024
Toeplitz Hashing is a class of functions in the 2-universal hash function family, that is widely adopted in quantum secure applications, particularly for the privacy amplification in quantum key distribution to generate secret keys, and as a strong randomness extractor for the quantum random number generators. In this work, we have investigated the preliminary implementation of Toepltiz hashing on processors, co-processors, and system-on-chip (SoC). We have implemented the fast-Fourier transform (FFT)-based Toepltiz hashing on Intel Xeon Cascade-lake 8268 processor and NVIDIA Tesla V100 GPU compute hardware. We have also implemented the binary multiplication-based Toeplitz hashing on the AMD Xilinx ZCU102 FPGA evaluation kit. Further, we present an example of heterogenous computing, by combining an Intel Core i7 CPU with the VEGA ET1031-based Aries v2.0 development board. Finally, we report, for the first time, an implementation of convolution of two matrices on an indigenously designed RISC-V VEGA SoC. Further, we have compared the implementation results following two approaches, i.e. normal matrix multiplication and the number theoretic transform (NTT) method. We report that there is a tenfold reduction in the computational time using the NTT method over the conventional method.
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Yamini S. Bute, G. H. Raisoni, Dept Cse G. H. Raisoni · 2012
Image compression is one of the major image processing techniques . Discrete wavelet transforms is the most popular transformation technique adopted for image compression. This paper presents an efficient VLSI architecture of a high speed, low power Discrete Wavelet Transform computing. There are number of architectures present for realizing DWT. Based on the application and the constraints imposed, the appropriate architecture can be chosen. Proposed DWT architecture uses DA-DWT scheme that is suitable on FPGA. The architecture has regular structure,simple control flow,small embedded buffers and low power consumption.
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Vaddiraju Venkata Satya Sreya, Lanka Mohan Satish, Velaga Hemu Sai et al. · Zenodo (CERN European Organization for Nuclear Research) · 2023
The convolutional neural network (CNN) is the most widely used machine learning technique within the fields of image and video processing. It is primarily used to categorize images using vast datasets. This require a lot of calculations. The effectiveness of a field-programmable gate array (FPGA) as a hardware accelerator for CNNs will give excellent performance at low power budgets. The employment of the Winograd algorithm can reduce the number of processing stages in CNN. 2-D convolution is employed for the bulk of calculations in CNNs. The tactic for computing convolution for smaller filter sizes that uses Winograd minimum filtering is the handiest. The comparison of computation complexity for multiplications will be performed using Matlab. The architecture of the Winograd-based processing element, RTL coding in Verilog HDL, and the test bench are designed to examine the performance. The Xilinx Vivado / Cadence tool will be used to implement the processing element in the convolution unit on an FPGA or ASIC.
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