Using Independent Component, Karthikesh Raju, Tapani Ristaniemi et al. · 2002
In this paper, Independent Component Analysis is considered for blind suppression of interference caused by bit-pulsed jamming in a direct sequence spread spectrum communication system. A framework for applying blind techniques to the jammer mitigation problem was earlier introduced in [1]. However, the scheme proposed there is based on second-order statistics only, and has serious practical limitations. For example, it fails for temporally uncorrelated data which is commonplace in CDMA communications. This paper extends the framework by taking into account both data modulation and temporally uncorrelated jamming, and removes the uncorrelatedness limitation by employing independent component analysis instead of second-order statistics. Computer simulations show that the proposed method performs better than the well-known RAKE method, which is the standard choice for suppressing jammer signals.
Cited by 0
Gang Ni, Chong He, Jingfeng Chen et al. · IEEE Transactions on Antennas and Propagation · 2021
A novel single-channel direction finding (DF) method with spatial spectrum estimation is proposed based on 1 bit time-modulated array (TMA). Its performance is analyzed from theoretical derivation to numerical simulations and compared with other existing DF methods. The proposed DF method is implemented as follows. First, the received sideband signals from the 1 bit modulated single-channel signal are deduced, followed by the detailed analysis of the received noise distribution. Second, the harmonic recovery (HR) method with the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$l_{2} $ </tex-math></inline-formula> -norm approximation is utilized to recover the original array signals. Finally, conventional spatial spectrum estimation methods are easily applied for high-accuracy DF. Meanwhile, The DF accuracy of the proposed 1 bit method is analyzed under the Gaussian noise model, and its Cramér–Rao lower bounds (CRLBs) are deduced for the first time and compared with conventional arrays and other DF TMA systems. Numerical simulations are provided to show that the proposed 1 bit TMA system and HR method can achieve better accuracy performance over the existing TMA systems when the circuit noise is predominant in the received noises. An <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$S$ </tex-math></inline-formula> -band 1 bit TMA system is fabricated and implemented to experimentally verify the feasibility of the proposed method under circumstances of a single incident source and two coherent sources.
Cited by 33
J.V. McCanny, R.A. Evans, J.G. McWhirter · Electronics Letters · 1986
We show how the architecture of two recently reported bit-level systolic array circuits—a single-bit coefficient correlator and a multibit convolver—may be modified to incorporate unidirectional data flow. This feature has some important advantages in terms of chip cascadability, fault tolerance and possible wafer-scale integration.
Cited by 42
Enhao Wang, Guangyao Peng, Zhi Hao Jiang · 2023
A 2-bit electronically reconfigurable reflect-array (RRA) element, integrated with two PIN diodes, is presented at Ka-band. The element can be adjusted to generate four states for 2-bit phase tuning. A dual-layer miniaturized structure is utilized to reduce the performance sensitivity of the element under obliquely incident waves, which is practical for large-aperture beam scanning applications. As a result, a 2-bit phase-shifting is achieved with a phase difference of <tex>$90^{\mathrm{o}}\pm 20^{0}$</tex> from 25.8 GHz to 26.3 GHz, possessing an averaged element loss of less than 0.9 dB. The RRA element is fabricated and measured based on the waveguide simulator. The good agreement between the measured and simulated results verifies the proposed design.
Cited by 1
Jinhyun Kim, Seongwoog Oh, Jungsuek Oh · IEEE Transactions on Antennas and Propagation · 2025
In this paper, a 2.5-bit polarization-rotating transmit array is proposed for ultra-wideband 6G terahertz communications. The transmit array utilizes a unit-cell structure combining a polarization rotator and a polarizer, enabling broadband phase tuning and impedance matching with 2.5-bit phase control. By applying single- and dual-bar topologies to the rotator, a low Q-factor matching controller was implemented, enabling low-transmission loss and wideband performance. Six types of unit cells were designed to realize 2.5-bit discrete phase states with a 260° tuning range. Arrangement of the unit cell was optimized based on the reference phase to minimize quantization loss, enabling optimal array configuration for high-efficiency beamforming. The fabricated 30 × 30 transmit array achieved a peak gain of 28.6 dBi, an aperture efficiency of 31.8%, and a 3 dB gain bandwidth of 46.5 GHz, 32.1%. Furthermore, the communication distance range was experimentally evaluated using error vector magnitude measurements with modulated signals, demonstrating increases of 3 times compared with that of a standalone horn antenna. Consequently, the proposed transmit array achieved a data rate of 1.44 Gbps at a distance of 100 cm, as confirmed by modulated signal throughput measurements.
Cited by 0
Shangyang Li, Yan Wang, Feng Xu · IEEE Transactions on Antennas and Propagation · 2022
In this article, an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8\,\,{\times }$ </tex-math></inline-formula> 8 array with 2-D wide-angle scanning is proposed and studied. By integrating two p-i-n diodes on the feeding line, the radiated electric field of the element can present two different phase states of 0° and −180°. By introducing the elaborately designed two groups of fixed phase delay (FPD) in horizontal and vertical directions, the grating lobe of the 1-bit array is effectively mitigated. Simulated and measured results indicate that the proposed array can cover the beam from −60° to 60° with no grating lobe within a 2-D scanning scope from 9 to 10 GHz. The peak gain of the array is 17.3 dBi and the cross-polarization level at the main lobe is less than −20 dB. The proposed array has the advantages of being lightweight, low-cost, and easy to integrate. These features enable its applications in space-limited scenarios such as base stations and unmanned aerial vehicles.
Cited by 25
Saeid Sedighi, Bhavani Shankar, Mojtaba Soltanalian et al. · Open Repository and Bibliography (University of Luxembourg) · 2021
Co-array-based Direction of Arrival (DoA) estimation using Sparse Linear Arrays (SLAs) has recently gained considerable attention in array processing thanks to its capability of providing enhanced degrees of freedom for DoAs that can be resolved. Additionally, deployment of one-bit Analog-to-Digital Converters (ADCs) has become an important topic in array processing, as it offers both a low-cost and a low-complexity implementation. Although the problem of DoA estimation form one-bit SLA measurements has been studied in some prior works, its analytical performance has not yet been investigated and characterized. In this paper, to provide valuable insights into the performance of DoA estimation from one-bit SLA measurements, we derive an asymptotic closed-form expression for the performance of One-Bit Co-Array-Based MUSIC (OBCAB-MUSIC). Further, numerical simulations are provided to validate the asymptotic closed-form expression for the performance of OBCAB-MUSIC and to show an interesting use case of it in evaluating the resolution of OBCAB-MUSIC.
Cited by 0Open access
Anjie Cao, Weifu Zhang, Hui Di et al. · 2021 13th International Symposium on Antennas, Propagation and EM Theory (ISAPE) · 2021
A digital-analog hybrid antenna array is proposed and verified with 2-bit time-modulators. Under different configurations, the antenna array can be set as phased array for transmitting and digital array for receiving. Its principle is as follows. For the transmitting, the 2-bit time-modulators concentrate most power to the first harmonic with equivalent single sideband (SSB) modulation. The phase differences among all the elements are controlled by added modulation sequences. For the receiving, the power of received signal is distributed to harmonics under periodic phase modulation. Then the array manifold is estimated from generated harmonics, and the direction of arrival (DOA) can be acquired by spatial spectrum estimation. The proposed structure breaks down the boundary between the analog array and digital array. Numeric simulations and experiments are provided to verify its effectiveness.
Cited by 0
Tianyuan Gu, Bohong Shu, Yuxiang Jiang et al. · 2024
Synthesis of beampattern with low-bit phase quantization is a worthwhile research problem in extensive applications. In this paper, we focus on minimizing the number of elements under the low-bit phase quantization constraint. After establishing a quantization-based beampattern synthesis model, a mixed-norm optimization problem is raised for sparse array construction. By solving the problem via reweighted ℓ<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</inf> norm approximation, optimal configuration of the sparse array is obtained. Simulation results verify the effectiveness of the proposed method with low-bit phase quantization.
Cited by 0
Neil Bergmann · 1989
The equations describing two spectral estimators for non-stationary signals - the Short-Time Fourier Transform and the Discrete Wigner Ville Distribution, and their implementations using the FIRST silicon compiler, based on bit-serial systolic array architectures is described. Both designs were simulated, and could achieve a speed of 500,000 3.2-point spectra per second. The performance of the DWM analyser is shown to be superior in terms of both spectral accuracy and chip count.
Cited by 0
Xiangping Meng, Jin Qian, Xin Qi · 2004
Association rule mining is one of the important data mining tasks. However, the previously proposed methods still encounter some problems, such as complex data structure, candidate set generation, and so on. To improve efficiency, association rules can be mined in parallel. In this paper, we use a simpler data structure called bit string array and propose a new approach to apply parallel projection and compress technique in parallel mining association rules. It conducts various operations on bit string array according to the frequency of frequent items. For frequent item with less frequency, we conduct set operation on them; for frequent item with more frequency, we adopt compress technique and conduct bit AND operator on them. Moreover, it will reduce the communication cost and also response time. This method can be scaled up to very large databases by parallel projection and compress technique.
Cited by 0
Jian-Qiao Han, Fanyi Meng, Yuhang Liu · 2024
In this paper, a series-fed circularly polarized (CP) 2-bit reconfigurable antenna array with fixed frequency beam steering is proposed. In the proposed antenna element, the corner truncated microstrip patch and the microstrip transmission line are located on both sides of the ground plane. Through two coupling feed slots located on the ground plane on both sides of the microstrip transmission line can enable the antenna element to achieve the phase states of 0° and -180°. By exciting the coupling slots on the same side with two feed points separated by a quarter of a wavelength on one side of the microstrip line, the phase states of 0° and -90° are obtained. Based on the 2-bit CP element, a ten-element series-fed CP array is designed to verify the design strategy at 26.0 GHz. The proposed CP array can achieve beam steering from -45° to 44°, with reflection coefficients of the array being less than -10dB.
Cited by 0
Yasin Azhdari, Mahmoud Farhang · 2025
Low-power and low-complexity Direction-of-Arrival (DOA) estimation is a critical challenge in various signal processing applications. This paper presents a data-driven approach using a neural network framework designed for single-snapshot, one-bit quantized measurements, enabling significant hardware simplification. We explore a Fully Connected (FC) Neural Network architecture (which is identical to a 1D convolutional architecture in the single-snapshot case) trained end-to-end on raw quantized data. The performance of this learned approach is rigorously compared against the well-established MUltiple SIgnal Classification (MUSIC) and Complex-valued Binary Iterative Hard Thresholding (CBIHT) algorithms. Our findings reveal that the proposed neural network achieves superior estimation performance compared to these, especially under low SNR values and in the presence of realistic array imperfections. We observe significant performance gains even without explicitly training the network on data with such imperfections, highlighting the generalization capabilities of the proposed method.
Cited by 0
Lu‐Yang Ji, Hong XiaoYue, Yifei Han et al. · IEEE Antennas and Wireless Propagation Letters · 2025
This work proposes an electrically tunable reconfigurable antenna array with wideband radiation and scattering modulation using a simpler structure and an easier control mechanism. A ladder-shaped patch is designed as the radiator. By inserting only one PIN diode in the middle of the patch structure, its operation can be modulated between a patch mode and a slot mode, achieving a wideband reflection phase difference of 180°±37°. A 4 × 4 array is formed using the aforementioned element, which can reconfigure its radiation and scattering modes by controlling the states of the PIN diodes. The measured results show that the proposed array exhibits a 10 dB impedance bandwidth of 20.99% with a peak gain of 14.94 dBi in the radiation mode. In the scattering mode, the phase distributions of the elements are optimized by the group search optimizer algorithm. The radar cross section (RCS) is reduced in the frequency range of 6 GHz to 20 GHz with an average RCS reduction value of 17 dB in the operating band.
Cited by 1
Abhinandan Sarkar, Jayabrata Chakrabarty, M Sheik Althaf · 2023
Periodic checking of health status for any system or sub-system is of paramount importance in Active Array Aperture Antennas. This is accomplished by reporting and presenting to the user the Built-In Test (BIT) information. But till date the amount of information that is presented as BIT is modest and insufficient for exhaustive analysis and troubleshooting. In this paper we present a novel scheme of exhaustive BIT collection for a system. Apart from the traditional Central BIT or CBIT, the collection of Power-On BIT or PBIT and Initiated BIT or IBIT presents a comprehensive picture of Active Array Antenna Unit (AAAU) at any instant. Since the Line Replaceable Units (LRUs) are over Ethernet Internet Protocol (IP) network, hence the properties of IP network are thoroughly used to advantage for BIT collection Secondly, given that the number of LRUs are in tens of thousands, hence it becomes necessary to sequence the BIT collection mechanism with respect to time and at the same time sufficient care must be taken to the fact that the BIT collection time should be kept as minimal as possible. We address all these challenges in our current design of BIT collection. The architecture is scalable and can be easily adapted to large aperture arrays.
Cited by 0
Xi Chen, Shaochen Li, Zhican Zhang et al. · 2025
Hybrid-domain CIMs [1]–[3] are attracting increasing attention nowadays as they combine the advantages of both digital CIMs (DCIM) [4]–[6] and analog CIMs (ACIM) [7]–[10], offering a more balanced choice. As depicted in Figure 14.6.1, when designing a hybrid CIM (HCIM), the first challenge to address is (1) the definition of boundary between the digital and analog part, which is determined by feature input mode and weight mapping. Prior HCIMs either utilized a bit-parallel in features to obtain high accuracy at the cost of hardware (HW) overhead [1] or realized a low HW overhead but suffered from accuracy loss due to error pollution problem (error of the analog partial sum makes the high precision digital partial sum of the same bit weight meaningless) with bit-serial scheme and specific weight mapping strategy [2], [5], neither of which provided a perfect solution to the boundary question. Therefore, we propose a bit-rotated feature-in scheme to address this challenge. To compress multiple multiplication results into one MAC result, several levels of shifters and adders are usually required, and the sign-bit needs to be considered when compressing signed and unsigned information. Unlike the bit-parallel/serial approach [1], [2], the bit-rotated scheme considers the sign-bit in the first product-wise adder, which induces (2) more digital overhead for sign-bit processing. Another challenge that continues to plague bit-rotated HCIM is (3) excessive energy wasted on low accuracy-contributed low-bit quantization in analog parts.
Cited by 16
Chung‐Yi Li, Chih‐Wen Lu, H. Jonathan Chao et al. · 2012
In this paper, an area-efficient successive approximation register (SAR) analog-to-digital converter (ADC) with a dithering V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ref</inf> is proposed. It reuses the capacitive array with the reconfiguration of V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ref</inf> to V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ref</inf> ± ΔV for reducing dramatically the ADC's area. The 2n resolution is achieved by the n bit SAR-ADC. To verify the proposed scheme, the proposed SAR ADC is implemented in a TSMC 0.18 μm 1P6M CMOS process with a supply voltage of 1.8V. The simulation results show that the capacitor area is reduced by 96% compared with the conventional 10-bit SAR-ADC. The ENOB of the proposed architecture is 9.767 bit when operating at 14MS/s.
Cited by 2
Chin-Liang Wang, Chi-Mo Hwang · 2002
A bit-level bit-serial systolic array is proposed for inner product computation. If data vectors are entered continuously and interleavedly, the proposed inner product array can be fully utilized for one of two operating modes: (1) computing two independent inner products concurrently, or (2) computing the sum of two inner products or an inner product with a double size. For a given data word length B, the system yields two outputs every 2B cycles for mode 1, ie, the average throughput is one per B cycle, and one output every 2B cycles for mode 2. The feature makes the inner product array more flexible for use in applications as compared to existing related systems. FIR filters based on the array are described for demonstration of its flexibility.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 2
Wujian Zhang, Zhou Runde, R. Kasai · 2002
This paper describes a new motion estimation algorithm, which combines with the hierarchical telescopic search method and adaptively selects the full or reduced bit-resolution image for block matching. Simulation results show that the proposed algorithm has low computational complexity and achieves good image quality. A novel systolic array with high throughput is specially developed.
Cited by 3
Geng-Cing Lin, Shao-Cheng Wang, Yi-Wei Lin et al. · 2012
We present an all-digital bit transistor characterization scheme for CMOS 6T SRAM array. The scheme employs an on-chip operational amplifier feedback loop to measure the individual threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ) of 6T SRAM bit cell transistors (holding PMOS, pull-down NMOS, and access NMOS) in SRAM cell array environment. The measured voltage is converted to frequency with dual VCO and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. A 512Kb test chip is implemented in 55nm 1P10M Standard Performance (SP) CMOS technology. Monte Carlo simulations indicate that the accuracy of the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> measurement scheme is about 2-7mV at TT corner across temperature range from 85°C to -45°C, and post-layout simulations show the resolution of the digital read-out scheme is <;60; 0.2mV per bit. Measured V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> distributions agree well with Monte Carlo simulation results.
Cited by 2