Daniel A. Reed, Ruth Aydt, Luiz DeRose et al. · 1998
Parallel computing is rapidly evolving to include heterogeneous collections of distributed and parallel systems. Concurrently, applications are becoming increasingly multidisciplinary with code libraries implemented using diverse programming models. To optimize the behavior of complex applications on heterogeneous systems, performance analysis software must also evolve, replacing post-mortem analysis with real-time, adaptive optimization, tightly integrating compile-time analysis with performance measurement and prediction, and supporting highmodality visualization and software manipulation. In this paper, we briefly survey the state of the art in each of these areas and sketch a series of open research problems. 1 Introduction As parallel computing evolves from homogeneous parallel systems to distributed collections of heterogenous systems (i.e., the computational grid), application developers face new and more complex performance tuning and optimization problems. Current users of pa...
Cited by 14
Natarajan, Chitra · Illinois Digital Environment for Access to Learning and Scholarship (University of Illinois at Urbana-Champaign) · 2015
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C R Krishna Kumar, Prahalad H A, Srigurunath Chakravarthi et al. · 2001
This paper describes on-going development of a performance analysis and tuning tool for parallel MPI [11] applications running on large clusters. Several parallel performance debugging tools such as VaMPIr [5], AIMS [3], and ParaVer [7] exist. Most of the existing tools provide post-mortem analysis and rely extensively on program visualization techniques to aid the user with performance bottleneck detection. Post-mortem analysis has limited utility for parallel programs that execute for several hours or days, and visualization of program flow can often be too complex to be useful for tuning applications executing on many processors (over 100 nodes). This work addresses the above-mentioned issues by providing real-time analysis and automatic performance bottleneck detection techniques using Artificial Intelligence (AI) techniques and a query-based interface. The tool uses J2EE technology [10] and a relational database to provide portable and secure real-time remote access to trace data that enables users to visualize and analyze parallel programs executing across the Internet using a web-browser. The tool will not only provide performance metrics for MPI applications, but will also detect bottlenecks arising from the MPI messaging layer. This work is envisaged to be particularly useful for performance tuning of parallel applications and messaging software on heterogeneous clusters.
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Wu, Xing · NCSU Libraries Repository (North Carolina State University Libraries) · 2013
WU, XING.Scalable Communication Tracing for Performance Analysis of Parallel Applications.(Under the direction of Frank Mueller.) Performance analysis and prediction for parallel applications is important for the design and development of scientific applications, and for the construction and procurement of highperformance computing (HPC) systems.As one of the most important approaches, application tracing is widely used for this purpose for being able to provide the computation and communication details of an application.Recent progress in communication tracing has tremendously improved the scalability of tracing tools and reduced the size of the trace file, and thereby opened up novel opportunities for trace-based performance analysis for parallel applications.This work focuses on domain-specific trace compression methodology and puts forth fundamentally new approaches to improve the communication tracing techniques.Facilitated by the advances in this area, novel algorithms are further designed to address the hard problem of performance analysis, prediction, and benchmarking at scale.Specifically, this work makes the following contributions:1.This work contributes ScalaExtrap, a fundamentally novel performance modeling scheme and tool.With ScalaExtrap, we synthetically generate the application trace for large numbers of MPI tasks by extrapolating from a set of smaller traces.We devise an innovative approach for topology extrapolation of SPMD (Single Program Multiple Data) codes with stencil or mesh communication.The extrapolated trace can subsequently be used for trace-based simulation, visualization, and detection of communication inefficiencies and scalability limitations at scale.2. This work contributes novel methods to automatically generate highly portable and customizable communication benchmarks from HPC applications.We utilize ScalaTrace to collect selected aspects of the run-time behavior of HPC applications.We then generate portable and easy-to-read benchmarks with identical run-time behavior from the collected traces with C and the rich-featured coNCePTuaL network benchmarking language.Because our approach supports code obfuscation, it is particularly valuable for proprietary, export-controlled, or classified applications. This work contributes novel algorithms to improve the trace compression and replayfor SPMD applications.Built on our past experience with ScalaTrace, a spectrum of compression techniques, including elastic data element representation, approximate loop matching, loop agnostic inter-node compression, and so on, are designed to improve the trace compression for applications with iteration-specific program behavior and diverging parallel control flow.A fully distributed replay tool for probabilistic traces is also developed for the reproduction of the computation performance of the original application.the memories of so many first times are still fresh: the first time fighting a twelve-hour jet lag in an operating systems class that I could not really understand, the first time sitting in Room 3266 struggling to comprehend a complication called ScalaTrace, the first time receiving a rejection for an ambitious paper submission, the first time standing behind a podium giving a conference presentation, the first time working in a national lab at an once secret location, the first time passing a job interview and getting a position in a dream company ... .Throughout the journey, there were disappointment, depression, frustration, and suffering, but there were also excitement, cheerfulness, brilliance, and most importantly, achievements, which are never possible without the encouragement, guidance, and support from the people to whom I shall show my gratitude.Firstly, I would like to thank my family.I thank my parents for supporting their only child to pursue a graduate degree in a country that is thousands of miles away.I thank my wonderful wife, Yi, for enduring the loneliness of being geographically apart for ten years, and for all the unselfish sacrifice thereafter.Their constant understanding and tremendous support encouraged me to move on.
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Casio P. Krebs, Guido Araújo, Lucas Wanner · 2025
Vector and matrix architectures accelerate workloads by exploiting data-level parallelism and reducing instruction overhead, but using them typically requires manual code changes. This work explores the Hwacha vector coprocessor and Gemmini matrix accelerator, alongside the BOOM superscalar RISC-V core, aiming to automate their activation. The SMR code rewriting tool was extended with libraries for data preparation, movement, and Hwacha/Gemmini activation for GEMV and GEMM. Integrated with Verilator, a simulation environment evaluated performance across seven Polybench kernels. Results show SMR can activate hardware accelerators without modifying the base code, enabling efficient acceleration more easily.
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Jinhui Zhao, Yang Jie · 2025
The vortex tube, a compact air-driven refrigeration device, shows promise for energy-efficient cooling. This study presents a novel bipolar, parallel vortex-tube design to address the performance limitations of single-stage vortex tubes under high inlet pressures. Through comprehensive numerical simulations, we evaluate the performance of a single-stage vortex tube, identifying a critical pressure threshold of approximately 1.1 MPa beyond which the system's energy separation efficiency degrades irreversibly. Our proposed dual-stage parallel design significantly enhances the inlet and cold-end mass flow rates, nearly doubling those of the single-stage configuration, while also managing the associated increase in cold-end temperature. The primary energy loss mechanism, viscous dissipation due to wall shear stresses, is identified as the main contributor to entropy generation within the system. This work provides a foundation for optimizing vortextube systems for industrial applications, offering a balanced approach to enhancing performance without compromising energy efficiency.
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Kalyani Bogineni · 1993
Photonic networks can support the high communication requirements of shared memory multiprocessors. A significant result of the high communication capacity is the simplification of the global address mapping problem. Distributed shared memory (DSM) approach integrates both shared memory and distributed memory system ideas to extract the strengths of each while balancing their respective weaknesses. Optical interconnections add the advantage of high-speed communication and provide very high bandwidth through wavelength division multiple access (WDMA). WDMA enables multiple multi-access channels to be formed on a single optical fiber. Access protocols are now required for arbitration of the multiple channels. This dissertation proposes multiprocessor architectures based on WDM interconnection networks and analyzes their performance. The design of parallel computers involves the design of two closely inter-related subsystems: the memory organization and the interconnection network.
The first part of the research involves the design of the memory organization. Two memory allocation schemes have been typically used in parallel computers: fixed memory allocation scheme (FMAS) and dynamic memory allocation scheme (DMAS). This dissertation shows that the photonic network of the system alleviates the traffic load concern, and enables the development of a fixed memory allocation scheme that has a lower complexity than the dynamic schemes. The proposed architectures are based on the uniform memory allocation scheme.
The second part of this research is the design of the photonic interconnection network: the network architecture and media access control (MAC) protocols. The optical network consists of many WDMA channels. WDM eases the data-rate and packet throughput speed mismatch between the photonic network and the interface electronics. The huge optical bandwidth is partitioned into multiple, more manageable, multi-access channels that each operate at the data-rate limited by the electronic interface. Network architectures and MAC protocols are proposed and investigated in this dissertation.
The interconnection network architecture and MAC protocols govern the feasibility of implementation of memory allocation and cache coherence schemes. The impact of MAC protocols on cache coherence schemes is studied in this dissertation. System size limitations due to optical power budget concerns can be overcome by using optical amplifiers and hierarchical structures. This dissertation proposes two such architectures and investigates their performance.
Analytical modeling techniques such as queueing models and semi-markov models are used in this dissertation. All the models are validated using discrete-event simulation.
Cited by 1
Georg Fleischmann, Matthias Gente, Fridolin Hofmann et al. · Parallel Computing · 1994
Cited by 2
Jacques Chassin de Kergommeaux, Uri Baron, W. Rapp et al. · Lecture notes in computer science · 1989
Cited by 3
Hong Tao Hou, Qun Li, Chao Wang et al. · Applied Mechanics and Materials · 2014
In this paper, we proposed a parallel simulation method for performance analysis of the Global Navigation Satellite System (GNSS) based on simulation model portability 2(SMP2) and service-oriented modeling method. GNSS is a space engineering system with a large-scale and complex structure, and the proposed method can be used to construct large complex simulation systems to gain the reusability, composability and interoperability of heterogeneous simulation resources. Firstly, the method including the conceptual framework, system architecture and system engineering process is introduced. Then the parallel model development, composition and schedule method are detailed respectively. Finally, a distributed M&S environment based on service-oriented SMP2 is designed, and an example of navigation system volume simulation is given to validate the whole method.
Cited by 0
Min Li, Tanja Van Achteren, Erik Brockmeyer et al. · Journal of Signal Processing Systems · 2009
Cited by 2
Xu Liu · Rice Digital Scholarship Archive (Rice University) · 2014
Parallel architectures have become common in supercomputers, data centers, and mobile chips. Usually, parallel architectures have complex features: many hardware threads, deep memory hierarchies, and non-uniform memory access (NUMA). \nProgram designs without careful consideration of these features may lead to poor performance on such architectures. First, multi-threaded programs can suffer from performance degradation caused by imbalanced workload, overuse of synchronization, and parallel overhead. Second, parallel programs may suffer from the long latency to the main memory. Third, in a NUMA system, memory accesses can be remote rather than local. \nWithout a NUMA-aware design, a threaded program may have many costly remote accesses and imbalanced memory requests to NUMA domains.\n\nPerformance tools can help us take full advantage of the power of parallel architectures by providing insight into where and why a program fails to obtain top performance. This dissertation addresses the difficulty of obtaining insights about performance bottlenecks in parallel programs using lightweight measurement techniques. This dissertation makes four contributions. \nFirst, it describes a novel performance analysis method for OpenMP programs, which can identify root causes of performance losses. Second, it presents a data-centric analysis method that associates performance metrics with data objects. This data-centric analysis can both identify both a program's problematic memory accesses and associated variables; this information can help an application developer optimize programs for better locality. Third, this dissertation discusses the development of a lightweight method that collects memory reuse distance to guide cache locality optimization. Finally, it describes implemented a lightweight profiling method that can help pinpoint performance losses in programs on NUMA architectures and provide guidance about how to transform the program to improve performance.\n\nTo validate the utility of these methods, I implemented them in HPCToolkit, a state-of-the-art profiler developed at Rice University. I used the extended HPCToolkit to study several parallel programs. Guided by the performance insights provided by the new techniques introduced in this dissertation, I optimized all of these programs and was able to obtain non-trivial improvements to their performance. The measurement overhead incurred by these new analysis methods is very small in both runtime and memory.
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Frank Mueller, Xing Wu · 2013
Performance analysis and prediction for parallel applications is important for the design and development of scientific applications, and for the construction and procurement of high-performance computing (HPC) systems. As one of the most important approaches, application tracing is widely used for this purpose for being able to provide the computation and communication details of an application. Recent progress in communication tracing has tremendously improved the scalability of tracing tools and reduced the size of the trace file, and thereby opened up novel opportunities for trace-based performance analysis for parallel applications.
This work focuses on domain-specific trace compression methodology and puts forth fundamentally new approaches to improve the communication tracing techniques. Facilitated by the advances in this area, novel algorithms are further designed to address the hard problem of performance analysis, prediction, and benchmarking at scale. Specifically, this work makes the following contributions:
1. This work contributes ScalaExtrap, a fundamentally novel performance modeling scheme and tool. With ScalaExtrap, we synthetically generate the application trace for large numbers of MPI tasks by extrapolating from a set of smaller traces. We devise an innovative approach for topology extrapolation of SPMD (Single Program Multiple Data) codes with stencil or mesh communication. The extrapolated trace can subsequently be used for trace-based simulation, visualization, and detection of communication inefficiencies and scalability limitations at scale.
2. This work contributes novel methods to automatically generate highly portable and customizable communication benchmarks from HPC applications. We utilize ScalaTrace to collect selected aspects of the run-time behavior of HPC applications. We then generate portable and easy-to-read benchmarks with identical run-time behavior from the collected traces with C and the rich-featured coNCePTuaL network benchmarking language. Because our approach supports code obfuscation, it is particularly valuable for proprietary, export-controlled, or classified applications.
3. This work contributes novel algorithms to improve the trace compression and replay for SPMD applications. Built on our past experience with ScalaTrace, a spectrum of compression techniques, including elastic data element representation, approximate loop matching, loop agnostic inter-node compression, and so on, are designed to improve the trace compression for applications with iteration-specific program behavior and diverging parallel control flow. A fully distributed replay tool for probabilistic traces is also developed for the reproduction of the computation performance of the original application. The respective design has been implemented in ScalaTrace 2, the next generation of the ScalaTrace tracing infrastructure.
Overall, this work is centered around scalable tracing of parallel applications. Built upon the prior research, it contributes novel approaches on communication trace compression and trace-based performance analysis. To the best of our knowledge, the algorithms and techniques proposed in this work are without precedence.
Cited by 0
Hanwei Chen, Jianwei Yin, Calton Pu · 2012
Parallel processing is an important pattern in cluster systems. To analyze the performance of parallel processing systems, we leveraged the fork-join queueing network (FJQN) models. However, there are no easy solutions to these models, especially for the multi-class closed ones. In this paper, a novel and efficient method named horizontal decomposition has been proposed. The main idea of our method is to approximate a non-product-form FJQN with some closed and open product-form networks. So the computational complexity can be dramatically reduced compared with the traditional hierarchical decomposition approach. And the algorithms for solving single-class and multi-class closed FJQNs have been developed respectively based on the horizontal decomposition. With these algorithms, the response time and throughput of each service center in a FJQN can be approximately calculated. The evaluation results show that 90 percentile of relative errors of most service centers are less than 15% except for the shared ones. The evaluation results also showed that the number of iterations in the algorithm for the multi-class FJQNs almost grows linearly with the population of networks.
Cited by 2
Holger Brunsta, Wolfgang E. Nagela · 2014
We have developed a distributed service architecture and an integrated parallel analysis engine for scalable trace based performance analysis. Our combined approach permits to handle very large performance data volumes in real-time. Unlike traditional analysis tools that do their job sequentially on an external desktop platform, our approach leaves the data at its origin and seamlessly integrates the time consuming analysis as a parallel job into the high performance production environment.
Cited by 0
Vinayak P Miskin, S S Kerur, Sumanth Y Kargar et al. · 2024
This paper presents a comparative analysis of delay performance in four distinct adder architectures: Brent-Kung, Ladner-Fischer, Han-Carlson, Kogge-Stone, and Ripple Carry Adder. Adders are fundamental components in digital circuits, crucial for efficient arithmetic operations in various computational systems. Each architecture employs unique design strategies to optimize carry propagation, influencing their overall speed and efficiency. The Ripple Carry Adder, with its straightforward sequential design, serves as a baseline for comparison, while the parallel-prefix architectures of Brent-Kung, Ladner-Fischer, Han-Carlson and Kogge-Stone Adders offer advanced solutions for reducing delay and improving Power-Efficiency. Through detailed simulations and analysis using Cadence Virtuoso, the Delay, Power-Efficiency and transistor count characteristics of each adder are evaluated, highlighting their strengths and tradeoffs. This study includes the design, simulation, and performance evaluation of these adder architectures using 90 nanometer technology, aiming to provide a comprehensive comparison that guides the selection of optimal adder designs for high-performance digital applications.
Cited by 1
Jing Song; Jong-I Mou; Calvin King · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 2008
Inverse and forward kinematic models were derived to analyze the performance of a parallel-chain hexapod machine. Analytical models were constructed for both ideal and real structures. Performance assessment and enhancement algorithms were developed to determine the strut lengths for both ideal and real structures. The strut lengths determined from both cases can be used to analyze the effect of structural imperfections on machine performance. In an open-architecture control environment, strut length errors can be fed back to the controller to compensate for the displacement errors and thus improve the machine's accuracy in production.
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Nölp, Klaus, Oden, Lena · Zenodo (CERN European Organization for Nuclear Research) · 2024
This repository enables performance analysis of parallel C++ programs in a JupyterLab environment using the xeus-cling notebook kernel.It features a JupyterLab extension (./jupyterlab_performance_display) that provides a graphical user interface for running experiments.The extension uses a C++ API (./performance) to run performance analysis tools like Score-P, Scalasca and Cube and creates visualizations.
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Mohr, B., Wolf, F. · JuSER (Forschungszentrum Jülich) · 2003
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Nic Series, Volume Isbn, Printer Graphische Betriebe et al. · 2002
Parallel computers with SMP nodes provide both multithreading and message passing as their modes of parallel execution. This thesis addresses the complexity of the performance problems that can arise in these systems by formally characterizing the problems in terms of execution patterns that represent situations of inefficient behavior. These patterns are specified as compound events which are input for an automatic analysis process that recognizes and quantifies the inefficient behavior in event traces. Mechanisms that hide the complex relationships within compound-event specifications allow a simple description of complex inefficient behavior on a high level of abstraction.
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