Kwang‐Ting Cheng, Li-C. Wang, Huawei Li et al. · 2016
This chapter focuses on automatic test pattern generation (ATPG). Historically, ATPG has focused on a set of faults derived from a gate-level fault model. For a given target fault, ATPG consists of two phases: fault activation and fault propagation. The objective of ATPG is to find an input sequence that, when applied to the circuit, enables testers to distinguish between the correct circuit behavior and the faulty circuit behavior caused by a particular fault. Effectiveness of ATPG is measured by the fault coverage achieved for the fault model and the number of generated vectors, which should be directly proportional to test application time. ATPG efficiency is another important consideration. The chapter describes circuit-based Boolean satisfiability techniques for solving circuit-oriented problems. It presents advanced ATPG research topics, such as for delay faults, crosstalk, and power supply noise. The chapter discusses ATPG for design applications including logic optimization and design verification.
Cited by 2
Kwang‐Ting Cheng, Li-C. Wang, Huawei Li et al. · 2016
This chapter focuses on automatic test pattern generation (ATPG). Historically, ATPG has focused on a set of faults derived from a gate-level fault model. For a given target fault, ATPG consists of two phases: fault activation and fault propagation. The objective of ATPG is to find an input sequence that, when applied to the circuit, enables testers to distinguish between the correct circuit behavior and the faulty circuit behavior caused by a particular fault. Effectiveness of ATPG is measured by the fault coverage achieved for the fault model and the number of generated vectors, which should be directly proportional to test application time. ATPG efficiency is another important consideration. The chapter describes circuit-based Boolean satisfiability techniques for solving circuit-oriented problems. It presents advanced ATPG research topics, such as for delay faults, crosstalk, and power supply noise. The chapter discusses ATPG for design applications including logic optimization and design verification.
Cited by 0
Cheng, Tim Kwang-Ting, Wang, Li-C, Li, Huawei et al. · Rare & Special e-Zone (The Hong Kong University of Science and Technology) · 2016
This chapter focuses on automatic test pattern generation (ATPG). Historically, ATPG has focused on a set of faults derived from a gate-level fault model. For a given target fault, ATPG consists of two phases: fault activation and fault propagation. The objective of ATPG is to find an input sequence that, when applied to the circuit, enables testers to distinguish between the correct circuit behavior and the faulty circuit behavior caused by a particular fault. Effectiveness of ATPG is measured by the fault coverage achieved for the fault model and the number of generated vectors, which should be directly proportional to test application time. ATPG efficiency is another important consideration. The chapter describes circuit-based Boolean satisfiability techniques for solving circuit-oriented problems. It presents advanced ATPG research topics, such as for delay faults, crosstalk, and power supply noise. The chapter discusses ATPG for design applications including logic optimization and design verification.
Cited by 0
2006
The complexity of VLSI devices increases rapidly as technology increases, resulting in an increase in the difficulty of test generation. Traditional test generation algorithms target one fault of a fault set at a time to generate a test. This paper presents a brief overview of a few different approaches to concurrent test generation. Concurrent test generation is the process of generating tests by “concurrently” targeting multiple faults.
Cited by 0
Sneh Saurabh · 2023
Chip designing is a complex task that requires an in-depth understanding of VLSI design flow, skills to employ sophisticated design tools, and keeping pace with the bleeding-edge semiconductor technologies. This lucid textbook is focused on fulfilling these requirements for students, as well as a refresher for professionals in the industry. It helps the user develop a holistic view of the design flow through a well-sequenced set of chapters on logic synthesis, verification, physical design, and testing. Illustrations and pictorial representations have been used liberally to simplify the explanation. Additionally, each chapter has a set of activities that can be performed using freely available tools and provide hands-on experience with the design tools. Review questions and problems are given at the end of each chapter to revise the concepts. Recent trends and references are listed at the end of each chapter for further reading.
Cited by 2
Rolf Drechsler, Görschwin Fey · Lecture notes in computer science · 2006
Cited by 5
Constraint Programming Sebastian, Sebastian Brand · 2007
The problem of automatic test pattern generation for sequential digital circuits is considered from the point of view of constraint programming.
Cited by 0
G.E. Taylor, B. R. Bannister, Pam Miller · 1989
Of the four main techniques for the automatic generation of test patterns for digital circuits the authors discuss algebraic techniques. The most widely known algebraic technique is that of Boolean Difference in which boolean functions G(X), F(X) describing the fault free and faulty circuits respectively are produced. A test function T(X) is formed from the exclusive-OR of G(X) and F(X). As an alternative to forming the complete test set and post processing to determine an appropriate test sequence, patterns which test for particular faults may be selected directly from the table. If, for example, a go/no-go test set is required a useful heuristic is to first find a pattern which detects a fault among those with lowest testability. Using either the fault augmented function (via evaluation of a small subset of its truth table) or fault simulation techniques other faults detected by the chosen pattern can be determined and eliminated from the table describing A(X,F). This process is then repeated for one of the remaining faults until a full fault cover has been obtained.
Cited by 0
El-Maidi, Elmostafa · OpenGrey (Institut de l'Information Scientifique et Technique) · 1988
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J.M.C. Geada, G. Russell · 1991
The increased levels of integration of VLSI circuits is causing problems associated with testing in two main areas. First, the continual growth in circuit complexity is constantly outpacing the capabilities of current gate level Automatic Test Pattern Generators (ATPG) to produce effective test patterns economically for production testing; to overcome this problem much research work is being directed at developing test pattern generation techniques at higher levels of abstraction. Second, the reduction of basic transistor dimensions is rendering the operation of the circuits more susceptible to intermittent faults. In the past the problems of production testing and intermittent fault detection have always been considered separately. However, recent research into Concurrent Error Detection (CED) techniques for detecting intermittent faults in safety-critical VLSI circuits has also suggested that some of the hardware used to implement the CED scheme, in particular the embedded checkers, could also be used to good advantage by ATPG programs during the generation of vectors for normal production testing of circuits, thus reducing the CPU time. >
Cited by 0
Wei Li, Yan Zou, Yixin Liang et al. · ArXiv.org · 2025
Modern IC complexity drives test pattern growth, with the majority of patterns targeting a small set of hard-to-detect (HTD) faults. This motivates new ATPG algorithms to improve test effectiveness specifically for HTD faults. This paper presents DEFT (Differentiable Automatic Test Pattern Generation), a new ATPG approach that reformulates the discrete ATPG problem as a continuous optimization task. DEFT introduces a mathematically grounded reparameterization that aligns the expected continuous objective with discrete fault-detection semantics, enabling reliable gradient-based pattern generation. To ensure scalability and stability on deep circuit graphs, DEFT integrates a custom CUDA kernel for efficient forward-backward propagation and applies gradient normalization to mitigate vanishing gradients. Compared to a leading commercial tool on two industrial benchmarks, DEFT improves HTD fault detection by 21.1% and 48.9% on average under the same pattern budget and comparable runtime. DEFT also supports practical ATPG settings such as partial assignment pattern generation, producing patterns with 19.3% fewer 0/1 bits while still detecting 35% more faults. These results indicate DEFT is a promising and effective ATPG engine, offering a valuable complement to existing heuristic.
Cited by 0Open access
Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey et al. · DROPS (Schloss Dagstuhl – Leibniz Center for Informatics) · 2009
Due to the rapidly growing size of integrated circuits, there is a need for new algorithms for Automatic Test Pattern Generation (ATPG). While classical algorithms reach their limit, there have been recent advances in algorithms to solve Boolean Satisfiability (SAT). Because Boolean SAT solvers are working on Conjunctive Normal Forms (CNF), the problem has to be transformed. During transformation, relevant information about the problem might get lost and therefore is not available in the solving process. In the following we briefly motivate the problem and provide the latest developments in the field. The technique was implemented and experimental results are presented. The approach was combined with the ATPG framework of NXP Semiconductors. Significant improvements in overall performance and robustness are demonstrated.
Cited by 0Open access
Wei Li, Yan Zou, Yixin Liang et al. · arXiv (Cornell University) · 2025
Modern IC complexity drives test pattern growth, with the majority of patterns targeting a small set of hard-to-detect (HTD) faults. This motivates new ATPG algorithms to improve test effectiveness specifically for HTD faults. This paper presents DEFT (Differentiable Automatic Test Pattern Generation), a new ATPG approach that reformulates the discrete ATPG problem as a continuous optimization task. DEFT introduces a mathematically grounded reparameterization that aligns the expected continuous objective with discrete fault-detection semantics, enabling reliable gradient-based pattern generation. To ensure scalability and stability on deep circuit graphs, DEFT integrates a custom CUDA kernel for efficient forward-backward propagation and applies gradient normalization to mitigate vanishing gradients. Compared to a leading commercial tool on two industrial benchmarks, DEFT improves HTD fault detection by 21.1% and 48.9% on average under the same pattern budget and comparable runtime. DEFT also supports practical ATPG settings such as partial assignment pattern generation, producing patterns with 19.3% fewer 0/1 bits while still detecting 35% more faults. These results indicate DEFT is a promising and effective ATPG engine, offering a valuable complement to existing heuristic.
Cited by 0Open access
Nishant Agrawal · International Journal for Research in Applied Science and Engineering Technology · 2021
Quantum computing is an exciting new field in the intersection of computer science, physics and mathematics. It refines the central concepts from Quantum mechanics into its least difficult structures, peeling away the complications from the physical world. Any combinational circuit that has only one stuck at fault can be tested by applying a set of inputs that drive the circuit to verify the output response. The outputs of that circuit will be different from the one desired if the faults exist. This project describes a method of generating test patterns using the Boolean satisfaction method. First, the Boolean formula is constructed to express the Boolean difference between a fault-free circuit and a faulty circuit. Second, the Boolean satisfaction algorithm is applied to the formula in the previous step. The Grover algorithm is used to solve the Boolean satisfaction problem. The Boolean Satisfiability problem for Automatic Test Pattern Generation(ATPG) is implemented on IBM Quantum Experience. The Python program initially generates the boolean expression from the file and converts it into Conjunctive Normal Form(CNF) which is passed on to Grover Oracle and runs on IBM simulator and produces excellent results on combinational circuits for test pattern generation with a quadratic speedup. Grover’s Algorithm on this problem has a run time of O(√N).
Cited by 0Open access
Bryan J. Heard, Ramu N. Sheshadri, Ronald B. David et al. · 1984
A general description of asynchronous sequential circuits and their testability problems is given. A set of hardware modifications and software modelling techniques is described which allow asynchronous circuits to be tested by scan design techniques.
Cited by 5
Zhang, Lizi, Davoodi, Azadeh · Zenodo (CERN European Organization for Nuclear Research) · 2024
The project "NN-for-ATPG" proposes a hybrid approach for Automatic Test Pattern Generation (ATPG) by integrating machine learning with the FAN algorithm. It includes implementations of two approaches, NN-Hyb and NN-All. It features two implementations, NN-Hyb and NN-All, which apply neural network models at selective and all circuit levels, respectively. Project files support the paper by providing the source code, circuit files, and scripts needed to reproduce key results, including comparisons for "all fault cases," "hard-to-detect faults," and runtime comparisons with and without acceleration. Minimal requirements include a C++ compiler and shell script execution capabilities.
Cited by 0Open access
Stephanie Hamilton · 1988
A new implication algorithm is described for automatic test pattern generation algorithms. Increased efficiency is gained by analyzing reconvergent fanouts and discovering new implications. The new algorithm is easy to implement and significantly increases the performance of ATPG for circuits which the ATPG algorithm previously badly.
Cited by 0
Journal of International Crisis and Risk Communication Research · 1991
Test generation for combinational circuits is an important step in the VLSI design process. Unfortunately, the problem is highly computation-intensive and for circuits encountered in practice, test generation time can often be enormous. In this paper, we present a parallel formulation of the backtrack search algorithm called PODEM, which is a highly used algorithm for this problem. It is known that the sequential PODEM algorithm consumes most of its execution time in generating tests for 'hard-to-detect' (HTD) faults and is often unable to detect them even after a large number of backtracks. Our parallel formulation overcomes these limitations by dividing the search space and searching it concurrently using multiple processes. We present a number of experimental results and show that these match our theoretical results presented elsewhere. We show that the search efficiency of the parallel algorithm improves and even beats that of the sequential algorithm as the 'hardness' of a fault increases. We present speedup results and performance analyses of our formulation on a 128 processor Symult s2010 multicomputer. We also present preliminary results on a network of Sun workstations. Our results show that parallel search techniques provides good speedups as well as high fault coverage of the HTD faults in reasonable time when compared to the uniprocessor implementation. Our experimental validation of most of our theoretical results builds confidence in the following theoretical prediction: our parallel formulation of PODEM is highly scalable on a variety of commercially-available, large MIMD parallel processors (in additions to the ones with which we experimented).
Cited by 0Open access
Zhang, Lizi, Davoodi, Azadeh · Zenodo (CERN European Organization for Nuclear Research) · 2024
The project "NN-for-ATPG" proposes a hybrid approach for Automatic Test Pattern Generation (ATPG) by integrating machine learning with the FAN algorithm. It includes implementations of two approaches, NN-Hyb and NN-All. It features two implementations, NN-Hyb and NN-All, which apply neural network models at selective and all circuit levels, respectively. Project files support the paper by providing the source code, circuit files, and scripts needed to reproduce key results, including comparisons for "all fault cases," "hard-to-detect faults," and runtime comparisons with and without acceleration. Minimal requirements include a C++ compiler and shell script execution capabilities.
Cited by 0Open access
Dahmen, H.-C., Gläser, U., Vierhaus, H.T. · Publikationsdatenbank der Fraunhofer-Gesellschaft (Fraunhofer-Gesellschaft) · 1996
S.205-212
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