Batarseh, Majd Ghazi, Al-Hoor, Wisam, Huang, Lilly et al. · Journal of International Crisis and Risk Communication Research · 2009
This paper presents a new digital pulsewidth modulator (DPWM) architecture for field programmable gate array (FPGA)-based systems. The design of the proposed DPWM architecture is based on fully utilizing the digital clock manager (DCM) resources available on new FPGA boards. Furthermore, this architecture will also window-mask the DCM operationtoonly a portion of the switching period in order to decrease power dissipation. This proposed digital modulator technique allows for higher DPWM resolution with lower power consumption, the primary barrier to high switching frequency operation. The presented technique relies on power-optimized resources already existing on new FPGAs, and benefits from the inherit phase-shifting properties of the DCM blocks, which help in simplifying the duty cycle generation. The architecture can be applied to achieve different numbers of bits for the DPWM resolution designed for different dc-dc applications. The suggested architecture is first simulated, implemented, and experimentally verified on a Virtex-4 FPGA board. © 2009 IEEE.
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Journal of International Crisis and Risk Communication Research · 2009
This paper presents a new digital pulsewidth modulator (DPWM) architecture for field programmable gate array (FPGA)-based systems. The design of the proposed DPWM architecture is based on fully utilizing the digital clock manager (DCM) resources available on new FPGA boards. Furthermore, this architecture will also window-mask the DCM operation to only a portion of the switching period in order to decrease power dissipation. This proposed digital modulator technique allows for higher DPWM resolution with lower power consumption, the primary barrier to high switching frequency operation. The presented technique relies on power-optimized resources already existing on new FPGAs, and benefits from the inherit phase-shifting properties of the DCM blocks, which help in simplifying the duty cycle generation. The architecture can be applied to achieve different numbers of bits for the DPWM resolution designed for different dc-dc applications. The suggested architecture is first simulated, implemented, and experimentally verified on a Virtex-4 FPGA board.
Cited by 0Open access
Muthyala Sowmika, M. O. V. Pavankumar, Kiran Mannem et al. · AIP conference proceedings · 2023
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William J. Gaughan, Brian Butka · 2010
When using a Light Detection and Ranging (LIDAR) gun for civil engineering applications, anomalous data were observed. A laboratory system was developed to simulate ranging to moving targets in a controlled environment in order to study the anomalous data and the performance of the LIDAR gun. The laboratory system was found to require the ability to generate sub-nanosecond phase shifts which can be updated in real time. This capability is available in high-quality laboratory, but the required equipment was not available to the authors. This research examines the design and implementation of a low cost system. The final design uses an embedded processor for computation of the necessary phase shifts and possible anomalies and an FPGA system to generate the dynamic precision phase shifts.
Cited by 1
D. Ramesh Babu, S. Karunakaran · Asian Journal of Engineering and Applied Technology · 2014
The Digital pulse width modulators are used for digital control applications. When the requirement of clock frequency exceeds the required limit the switching frequency of the power converter also increased. In this paper a new architecture for digital pulse width modulator is proposed. The proposed method is based on digital clock manager which is present in the Spartan 3 FPGA. The architecture will be implemented in FPGA Spartan 3 and the performances are verified.
Cited by 1Open access
Gaurav Gupta, M. Tech Scholar Department, Sangeeta Nakhate Phd et al. · 2016
Digitization of modern world has led to increasing use of digital equipment. The pioneer equipment in this regard is Digital Pulse Width Modulators. Although there is limit on clock frequency which is to be used in digital circuit. This paper describes simple Digital Pulse Width Modulator with optimized Area using Field Programmable Gate Arrays (FPGA). The proposed architecture uses a phase shifter mechanism provided by on chip Digital Clock Manager (DCM) in FPGA. The circuit uses such design to reduce cell Area to greater limit. The design is experimentally tested and compared with other design.
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Jonas Lienke, Florian Kögler, Eric Schäfer et al. · 2024
The design of clock management circuitry is currently done using a more or less analog design flow. For a current chip design, we show a fully-digital implementation of a digital clock manager (DCM) block that generates a clock signal from a reference clock. It utilizes a PLL-like structure for self-calibration and is implemented purely in Verilog. Since the DCM is designed only in synthesizable Verilog, it eliminates the need for an analog simulation and enabling automated synthesis and layout. We verify our circuit using a standard digital simulation method with annotated timings extracted from the layout. The DCM is implemented in a commercial 350 nm CMOS technology using $0.138 \mathrm{~mm}^{2}$. In our scenario, it creates a clock of 70 MHz from a reference clock of 5 MHz with a jitter of 30 ps.
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V. Radhika, K. Baskaran · 2016
This paper deals with hybrid Digital Pulse Width Modulator (DPWM) architecture to generate a variable duty cycle pulse to control the switch of power converters. The proposed architecture highly utilizes the logic blocks present in Field Programmable Array (FPGA) to derive the variable duty cycle Pulse Width Modulation (PWM) pulses. This architecture uses the clock multiplying capability of on chip Digital Clock Manager (DCM) present in FPGA to derive clock frequency doubled of input clock frequency which minimizes the usage higher external clock frequency. The proposed design uses the gray encoding mechanism combined with a decoder to derive a variable duty pulse rather than a binary encoding scheme and a comparator used in traditional DPWM architectures. This approach minimizes the power consumption and best utilizes the logic resources available in FPGA. The design is tested experimentally with low cost SPARTAN 3A and results are shown in Digital storage Oscilloscope.
Cited by 4
Anupama. S · 2014
Abstract- Pulse width modulators are widely used in power electronic applications for controlling power converters. Pulse width modulators are the basic building block in digital control architectures of any power converters. Nowadays recent developments in semiconductor technology enable the use of high switching frequencies. So the design of power converters requires a high resolution high frequency pulse width modulators (HRPWMs) inorder to reduce the size and cost, and improved dynamic behavior and power density. The resolution of pulse width modulator determines the accuracy in the output current/voltage. The high resolution pulse width modulators is to be designed based on the on-chip Digital Clock Manager block present in the lowcost Spartan-3 FPGA series and on the I/O delay element(IODELAYE1) available in the high end virtex-6 FPGA series. These architectures are designed and compared to analyze the performance. Index Terms- Digital clock manager,Field programmable gate arrays (FPGA),IODELAYE1,power conversion, Pulse Width Modulators. 1.
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Nick Sawyer, N Bits · 2009
When designing digital systems, there is often a requirement to synchronize incoming data and clock signals with an internal system clock, i.e., the internal and external clock are at exactly the same frequency, but due to variable backplane, board, or application-specific standard product (ASSP) delays, the phase relationship is not known. The circuit described in this application note addresses this issue for both single traces and data buses up to 210 MHz in a Virtex®-II-5 device. The speed limitation is imposed by the maximum frequency that can be accepted by the Digital Clock Manager (DCM), in a mode where it is capable of providing both a new clock and a new clock shifted by 90 degrees. The maximum speed would be 210 MHz in a Virtex-II-5 device or a Virtex-II Pro-6 device, and around 160 MHz in a Spartan®-3 generation device. A typical application is shown in Figure 1.
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V. Radhika, K. Baskaran, K. Srinivasan · International Journal of Recent Technology and Engineering (IJRTE) · 2019
DC-DC converters are electronic devices that are used to change DC electrical power efficiently from one voltage level to another. This paper proposes a new Digital Pulse Width Modulator (DPWM) which generates variable duty cycle PWM pulse and it can be used as switching controller for DC-DC converters used in battery powered portable electronic and mobile devices. DPWM utilizes the advantage of Digital Clock Manager (DCM) present in FPGA to multiply the clock frequency to eliminate the clock skew. The proposed DPWM uses the four bit gray counter and one hot encoder with SR flip flop to generate the PWM pulse whose duty cycle can be varied according to the control signal. To verify the results DPWM was implemented in SPARTAN 3A.
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Hesham Omran, Khaled Sharaf, Magdy M. Ibrahim · 2009
In this paper an all-digital pulse output direct digital synthesizer (DDS) is described. The synthesizer is fully implemented on FPGA and does not require any external analog components. Selective over-sampling and tapped delay line are used to reduce jitter and improve spectral performance. Selective over-sampling relaxes the requirements on the delay line with a minor effect on power consumption and circuit complexity. The delay line is implemented using the FPGA digital clock manager (DCM). The synthesizer generates clock signals with maximum output frequency up to f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">clk</sub> . It achieves sub-Hz resolution and sub-¿s switching time. Experimental measurements validate system operation with spurious free dynamic range (SFDR) greater than 40 dB.
Cited by 19
2005
The Virtex™-II Pro family meets the requirements of high-performance double data rate (DDR) designs. This application note provides implementation guidelines for DDR interfaces using a Digital Clock Manager (DCM) and local inversion clocking techniques for Virtex-II Pro devices. It also describes the requirements for using the corner DCMs in an XC2VP100 –6 device above 360 MHz.
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PengXiang Wang, Jinmei Lai · 2012
A novel Delay Manager (DM) based on the Digital DLL designed to adjust the delay time of the FPGA's IO port is proposed. The DDLL leverage the oversample mechanism to achieve high integration density and low power. A novel gear-shift component is utilized for both fast and precise locking in. To be adequate for digital data transmit, a new full-swing delay cell with good edge matching performance is used and the non-linearity is compensated with a nonlinear resister ladder DAC. Fabricated in a 65nm digital CMOS process, the simulation results show that the proposed architecture can operate at 50MHz with 256 non-invert delay-cell stages in line and the lock latency is one clock cycle. So the highest resolution of the Delay Manager can be as low as 78ps.
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Peter Moris · KTH Publication Database DiVA (KTH Royal Institute of Technology) · 2015
Development of the VHDL firmware for a high-speed Analogue to Digital Converter (ADC) is the focus of this paper, including writing, debug- ging and evaluation of said firmware. The finished version of the firmware is able to correctly convert analogue signals received by the ADC into their digital representations. This result requires fully functional Phase Locked Loop, Clock Manager, ADC Wire/SERDES and ADC components, as well as functioning Phase Delay and Bitslip algorithms, all of which are discussed in this paper.
Cited by 0Open access
Jim Tatsukawa · 2008
Consumer Display applications like flat-panel displays and video players commonly use highspeed Low Voltage Differential Signaling (LVDS) interfaces to transfer video data. To address Electromagnetic Compatibility (EMC) issues, spread-spectrum clocking can be used to reduce th impact of radiated energy produced by these signals. When a spread-spectrum clock is used as the source from which these signals are derived, the radiated energy is spread across a range of frequencies, effectively reducing the peak energy at any one frequency. This application note shows that a spread-spectrum clock will drive the LVDS interfaces of Spartan®-3E and Extended Spartan-3A family devices with no adverse effects on a system&apos;s performance. It describes how to estimate the maximum spread-spectrum clock modulation frequency for the Digital Clock Manager (DCM) and describes a simple test setup to evaluate the effects of the spread-spectrum clock on a typical LVDS communications path.
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Nguyễn Văn Toán, Dam Minh Tung, Jeong‐Gun Lee · IEICE Electronics Express · 2017
In this paper, we propose a new method for measuring metastability in the mutual exclusion element (MUTEX) implemented on a Field Programmable Gate Array (FPGA). Our method uses fine-grained phase shifts of a digital clock manager to trigger Flip-Flops to generate concurrent inputs for a MUTEX. By dynamically adjusting the phase shift between two clock signals, we can force the MUTEX into a metastable state. The benefit of our approach is that it is easier to force the MUTEX become metastable compared to the conventional approach using two un-correlated signals. The experiments have been performed on a Xilinx Spartan-6 (XC6SLX9-4TQG144C).
Cited by 4Open access
C. N. Marimuthu, B. Priyanka · 2023
Currently, cybersecurity plays a crucial role in various fields to ensure secure data communication. True Random Number Generators (TRNGs) are crucial components for many critical security applications. While analog-based entropy sources are often used in digital-based solutions, there is a high demand for digital-based solutions, especially for Field Programmable Gate Array (FPGA)-based digital systems. A unique technique has been developed to simplify the design of TRNGs on FPGA devices. This technique utilizes the runtime capabilities of the hardware primitives provided by the Digital Clock Manager (DCM) to adjust the phase shift between two clock signals. An auto-tuning approach automatically adjusts the phase difference between the clock signals to force one or more flip-flops (FFs) to enter the metastability zone, which is used as a source of unpredictability in the system. Additionally, the fast carry-chain hardware primitive is uniquely used to further enhance the randomness of the generated bits. Lastly, a powerful on-chip post-processing strategy is employed to prevent any interference with the TRNG output. This work was implemented in verilog HDL, with 32 and 64 data width, and synthesized in Xilinx Zynq FPGA. The characteristics of the TRNG design were evaluated based on area, delay, and power consumption.
Cited by 1
Ángel Quirós‐Olozábal, Juan Manuel Barrientos-Villar, María-Ángeles Cifredo-Chacón · 2009
This paper presents a time-to-digital converter based on Virtex FPGA's reconfiguration and phase shifting capabilities. Concretely, the converter is built around a Digital Clock Manager, and phase shift is the module's characteristic that is modified through reconfiguration. The proposed conversion method shifts an internally generated clock signal's phase to precisely determine the position of a target event in the measuring signal. These phase shifts are performed following a process that is similar to successive approximation analog-to-digital conversion. Using the proposed method a resolution of less than 140 ps can be achieved using a Xilinx's Virtex-4 FPGA. The converter can be implemented in a FPGA without needing any other component, does not require manual placement or routing for implementation, nor does it require an external calibration process. This circuit can be used in any application that demands a precise measurement of a static delay introduced by an external system.
Cited by 2
Naoki Fujieda, Sogo Takashima · 2020
A True Random Number Generator (TRNG) using a pair of Phase-locked Loops (PLLs) or Digital Clock Managers (DCMs) has an advantage of minimal usage of logic elements of FPGA. This paper focuses on a new clocking element of Xilinx FPGAs called mixed-mode clock manager (MMCM) and presents its effective use for better randomness and higher throughput. According to an evaluation on an Artix-7 FPGA using 132 sets of parameters, 89 sets passed AIS-31 Procedure B with the proposed method, while only 9 sets passed when simply porting an existing DCM-based method. The average throughput was 1.18 Mbit/s, which was 5x faster than an existing DCM-based method.
Cited by 2