2010 - 2011 Gate Count
University Libraries · ResearchWorks at the University of Washington (University of Washington) · 2011
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About 3,393 papers for “Gate count”
University Libraries · ResearchWorks at the University of Washington (University of Washington) · 2011
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Omar Ghoniem, Hatem Elsayed, Hassan Soubra · 2023
In recent years, interest in quantum computers has grown significantly. While commercial quantum computers are not available yet, both private and public sector investment into developing quantum computers has developed considerably. One of the key challenges in quantum computing is optimizing the performance of the quantum hardware devices. Different factors can be put into consideration regarding this point, including the number of gates used by the processors to execute different quantum computations and operations. This paper focuses on developing quantum hardware metrics that can be used to measure the performance of a quantum processor in terms of number of quantum gates needed to execute different quantum algorithms. The proposed metrics have been implemented and experimental evaluations have been conducted on various IBM back-end Quantum Computers and using 4 different algorithms: a 5-Qubit entangled circuit algorithm, a 5-Qubit implementation of Grover’s quantum search algorithm, a 5-Qubit implementation of Simon’s quantum algorithm and the 7-Qubit implementation of Steane’s error correction quantum algorithm. In addition, quantitative data on the number of quantum gates used by quantum processors to execute the different quantum algorithms were gathered, which enabled the analysis of how the availability and compatibility of different gate sets affect the overall number of quantum gates needed in the execution of the different quantum algorithms.
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Ruth Shumate · 2016
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University Libraries, UW · ResearchWorks at the University of Washington (University of Washington) · 2010
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University Libraries · ResearchWorks at the University of Washington (University of Washington) · 2010
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Soichiro Yamazaki, Seiseki Akibue · arXiv (Cornell University) · 2026
Controlled gates are key components in various quantum algorithms. Improving on the prior work of Gosset et al., we show that, for an allowed error $\varepsilon$, $3\log_2(1/\varepsilon) + o(\log(1/\varepsilon))$ $T$ gates are sufficient to approximate most multi-qubit controlled SU(2)s. We also show that this T-count matches the lower bound when the use of an almost controlled gate is prohibited. As an application, general controlled gate synthesis and efficient SU(4) gate synthesis are given.
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Soichiro Yamazaki, Seiseki Akibue · arXiv (Cornell University) · 2026
Controlled gates are key components in various quantum algorithms. Improving on the prior work of Gosset et al., we show that, for an allowed error $\varepsilon$, $3\log_2(1/\varepsilon) + o(\log(1/\varepsilon))$ $T$ gates are sufficient to approximate most multi-qubit controlled SU(2)s. We also show that this T-count matches the lower bound when the use of an almost controlled gate is prohibited. As an application, general controlled gate synthesis and efficient SU(4) gate synthesis are given.
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Marko Maležič, Johann Ostmeyer · ArXiv.org · 2026
Hamiltonian formulations of lattice field theories provide access to real-time dynamics, but their simulation is difficult to implement efficiently. Trotter-Suzuki decompositions are at the center of time evolution computation, either on quantum hardware or classically, for instance with the use of tensor networks. While low-order Trotterizations remain the standard choice due to their simplicity, higher-order schemes offer the potential for improved efficiency. In this work we outline a short guide to Trotter-Suzuki schemes and their implementations in general. To help with this, we highlight new efficient schemes found by our optimization framework, and demonstrate their performance on the Heisenberg model.
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Marko Maležič, Johann Ostmeyer · arXiv (Cornell University) · 2026
Hamiltonian formulations of lattice field theories provide access to real-time dynamics, but their simulation is difficult to implement efficiently. Trotter-Suzuki decompositions are at the center of time evolution computation, either on quantum hardware or classically, for instance with the use of tensor networks. While low-order Trotterizations remain the standard choice due to their simplicity, higher-order schemes offer the potential for improved efficiency. In this work we outline a short guide to Trotter-Suzuki schemes and their implementations in general. To help with this, we highlight new efficient schemes found by our optimization framework, and demonstrate their performance on the Heisenberg model.
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Shinichi Kato, Minoru Watanabe · Lecture notes in computer science · 2009
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Daisaku Seto, Minoru Watanabe · 2008
Recently, to realize large real-time systems, demands for fast computation on large VLSI have continued to increase. An optically reconfigurable gate array has been developed to realize large virtual gates. As part of that research effort, the world's largest 11,424 gate-count dynamic optically reconfigurable gate array VLSI chip, which is based on a concept using junction capacitance of photodiodes as configuration memory, has been fabricated. The size and process of the VLSI chip are, respectively, a 96.04 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a 0.35 mum-3 metal CMOS process technology. To clarify the availability of the VLSI, this paper presents an experimental result of a long retention time of its photodiode memory architecture.
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Shigeru Yamashita, Takashi Horiyama, Norihito Yasuda et al. · 2025
This paper shows that the minimum number of Toffoli gates to realize any 4-input function is at most five for the first time as far as we know. This result should be not only theoretically interesting but also practically useful because sub-circuits to calculate 4-input functions are used in the practical quantum Boolean circuit design framework based on LUT-network synthesis, and the state-of-the-art heuristic method requires an average of 9.29 Toffoli gates to realize 4-input functions. Because previous SAT-based exact design methods cannot find the minimum number of Toffoli gates to implement a target function, we introduce a novel idea, complex Toffoli gates, which are very useful to significantly reduce the search space to find a quantum Boolean circuit with the minimum number of Toffoli gates; we can successfully formulate the problem as an SMT problem by using complex Toffoli gates, which should be interesting on their own.
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John J. Burke, Biswajit Basu, Ciarán McGoldrick · 2023
This work proposes an efficient quantum state preparation technique for non-independent 2D data. Demonstrated on the DCT, the method performs a change of basis on the data source, compresses it, prepares a quantum state to represent the compressed data, and performs the inverse basis change using an efficient quantum circuit, recreating the original source. We show how the gate count for a quantum circuit to prepare a state representing image data can be reduced by 75% achieving good image quality (PSNR 30), and by 50% retaining very good image quality (PSNR 40). The approach lends itself to achieving similar scale gate count reductions for other transforms, including those with efficient quantum circuit implementations (such as the QFT and QWT).
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David Poulin, Alexei Kitaev, Damian S. Steiger et al. · Physical Review Letters · 2018
We present two techniques that can greatly reduce the number of gates required to realize an energy measurement, with application to ground state preparation in quantum simulations. The first technique realizes that to prepare the ground state of some Hamiltonian, it is not necessary to implement the time-evolution operator: any unitary operator which is a function of the Hamiltonian will do. We propose one such unitary operator which can be implemented exactly, circumventing any Taylor or Trotter approximation errors. The second technique is tailored to lattice models, and is targeted at reducing the use of generic single-qubit rotations, which are very expensive to produce by standard fault tolerant techniques. In particular, the number of generic single-qubit rotations used by our method scales with the number of parameters in the Hamiltonian, which contrasts with a growth proportional to the lattice size required by other techniques.
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Diyi Liu, Shuchen Zhu, Guang Hao Low et al. · ArXiv.org · 2025
Efficient block encoding of many-body Hamiltonians is a central requirement for quantum algorithms in scientific computing, particularly in the early fault-tolerant era. In this work, we introduce new explicit constructions for block encoding second-quantized Hamiltonians that substantially reduce Clifford+T gate complexity and ancilla overhead. By utilizing a data lookup strategy based on the SWAP architecture for the sparsity oracle $O_C$, and a direct sampling method for the amplitude oracle $O_A$ with SELECT-SWAP architecture, we achieve a T count that scales as $\mathcal{\tilde{O}}(\sqrt{L})$ with respect to the number of interaction terms $L$ in general second-quantized Hamiltonians. We also achieve an improved constant factor in the Clifford gate count of our oracle. Furthermore, we design a block encoding that directly targets the $η$-particle subspace, thereby reducing the subnormalization factor from $\mathcal{O}(L)$ to $\mathcal{O}(\sqrt{L})$, and improving fault-tolerant efficiency when simulating systems with fixed particle numbers. Building on the block encoding framework developed for general many-body Hamiltonians, we extend our approach to electronic Hamiltonians whose coefficient tensors exhibit translation invariance or possess decaying structures. Our results provide a practical path toward early fault-tolerant quantum simulation of many-body systems, substantially lowering resource overheads compared to previous methods.
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M. Lavanya · International Journal of Advanced Research in Electrical Electronics and Instrumentation Engineering · 2014
Addition is the most fundamental computational process encountered in digital system. An area efficient carry select adder is proposed in this paper by comparing the Gate count of Regular and Modified 16-bit carry select adders with a proposed Common Boolean Logic carry select adder. In this paper, Gate count evaluation of Regular, Modified and proposed designs are given in terms of INVERTER, NAND and NOR Gates. The comparison results shows that the common Boolean logic carry select adder structure require lesser number of gates than that of Regular and Modified 16-bit carry select adder.
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Dave Wecker, Bela Bauer, Bryan K. Clark et al. · Physical Review A · 2014
As quantum computing technology improves and quantum computers with a small\nbut non-trivial number of N > 100 qubits appear feasible in the near future the\nquestion of possible applications of small quantum computers gains importance.\nOne frequently mentioned application is Feynman's original proposal of\nsimulating quantum systems, and in particular the electronic structure of\nmolecules and materials. In this paper, we analyze the computational\nrequirements for one of the standard algorithms to perform quantum chemistry on\na quantum computer. We focus on the quantum resources required to find the\nground state of a molecule twice as large as what current classical computers\ncan solve exactly. We find that while such a problem requires about a ten-fold\nincrease in the number of qubits over current technology, the required increase\nin the number of gates that can be coherently executed is many orders of\nmagnitude larger. This suggests that for quantum computation to become useful\nfor quantum chemistry problems, drastic algorithmic improvements will be\nneeded.\n
Cited by 299Open access
Nupur Jain, Biswajit Mishra, Peter Wilson · SN Applied Sciences · 2021
Abstract A new reconfigurable architecture for biomedical applications is presented in this paper. The architecture targets frequently encountered functions in biomedical signal processing algorithms thereby replacing multiple dedicated accelerators and reports low gate count. An optimized implementation is achieved by mapping methodologies to functions and limiting the required memory leading directly to an overall minimization of gate count. The proposed architecture has a simple configuration scheme with special provision for handling feedback. The effectiveness of the architecture is demonstrated on an FPGA to show implementation schemes for multiple DSP functions. The architecture has gate count of $$\approx$$ <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mo>≈</mml:mo> </mml:math> 25k and an operating frequency of 46.9 MHz.
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Christoffer Hindlycke, Jan-Åke Larsson · Physical Review Research · 2024
Building generic gates from a restricted gate set is a difficult but important problem, especially in the noisy regime where only a limited set of noise-resistant gates are available, e.g., fault-tolerant Clifford gates (generated by Hadamard, phase, and gates) and fault-tolerant Toffoli gates. The Toffoli is also often used as a building block of many algorithms and will need to be constructed if not directly available. This makes <a:math xmlns:a="http://www.w3.org/1998/Math/MathML"><a:mtext>Clifford</a:mtext><a:mo>+</a:mo><a:mtext>Toffoli</a:mtext></a:math> an attractive gate set for building generic gates. In this Letter we give a simple and efficient algorithm for building an approximate single-qubit rotation using only <b:math xmlns:b="http://www.w3.org/1998/Math/MathML"><b:mtext>Clifford</b:mtext><b:mo>+</b:mo><b:mtext>Toffoli</b:mtext></b:math>, which in turn enables any generic single-qubit unitary. An important difference compared to earlier attempts is that the use of the Toffoli allows us to use simple rounding as opposed to a complicated approximation algorithm. The resulting gate array does not rely on repeatedly applying a fixed rotation, but immediately applies a rotation <c:math xmlns:c="http://www.w3.org/1998/Math/MathML"><c:msub><c:mi>R</c:mi><c:msup><c:mi>θ</c:mi><c:mo>*</c:mo></c:msup></c:msub></c:math> that is <d:math xmlns:d="http://www.w3.org/1998/Math/MathML"><d:mi>ε</d:mi></d:math>-close to the desired rotation <e:math xmlns:e="http://www.w3.org/1998/Math/MathML"><e:msub><e:mi>R</e:mi><e:mi>θ</e:mi></e:msub></e:math>, with a success probability strictly greater than <f:math xmlns:f="http://www.w3.org/1998/Math/MathML"><f:mrow><f:mn>1</f:mn><f:mo>/</f:mo><f:mn>2</f:mn></f:mrow></f:math>. It can be rerun upon failure, giving an expected number of repetitions strictly less than 2, an expected Toffoli count strictly less than <g:math xmlns:g="http://www.w3.org/1998/Math/MathML"><g:mrow><g:mn>4</g:mn><g:mo>⌈</g:mo><g:mo form="prefix">log</g:mo><g:mstyle scriptlevel="0" displaystyle="false"><g:mfrac><g:mn>1</g:mn><g:mi>ε</g:mi></g:mfrac></g:mstyle><g:mo>⌉</g:mo></g:mrow></g:math>, an expected gate depth strictly less than <k:math xmlns:k="http://www.w3.org/1998/Math/MathML"><k:mrow><k:mn>4</k:mn><k:mo>⌈</k:mo><k:mo form="prefix">log</k:mo><k:mstyle scriptlevel="0" displaystyle="false"><k:mfrac><k:mn>1</k:mn><k:mi>ε</k:mi></k:mfrac></k:mstyle><k:mo>⌉</k:mo><k:mo>+</k:mo><k:mn>6</k:mn></k:mrow></k:math>, and uses <o:math xmlns:o="http://www.w3.org/1998/Math/MathML"><o:mrow><o:mn>2</o:mn><o:mo>⌈</o:mo><o:mo form="prefix">log</o:mo><o:mstyle scriptlevel="0" displaystyle="false"><o:mfrac><o:mn>1</o:mn><o:mi>ε</o:mi></o:mfrac></o:mstyle><o:mo>⌉</o:mo></o:mrow></o:math> ancillas. The small circuit depth of our construction enables low-noise gates on existing quantum computational devices, and allows for arbitrary precision using a very modest number of ancillas. Published by the American Physical Society 2024
Cited by 4Open access
Minoru Watanabe, Fuminori Kobayashi · 2014
High-speed reconfigurable processors have been developed in recent years: they are DAP/DNA chips and DRP chips [1][2]. These devices can be changed from one context to another context at every clock cycle in a few nanoseconds.
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