B.F. Cockburn, A.L.-C. Kwong · 2002
This paper presents simulation evidence supporting the use of bit transition maximization techniques in the design of hardware test pattern generators (TPGs). Bit transition maximization is a heuristic technique that involves increasing the probability that a bit will change values going from one test pattern to the next. For most of the ISCAS-85 benchmarks and many of the ISCAS-89 benchmarks bit transition maximization enhances the fault coverage of two-pattern faults such as gate delay faults and CMOS transistor stuck-open faults. It achieves these benefits without reducing the fault coverage with respect to classical stuck-at faults.
Cited by 1
Sanjeevikumar Padmanaban, Spyros Tragoudas · 2005
An approach for selecting critical paths along which testable path delay faults can exist is presented. The proposed method is particularly helpful on path intensive circuits. Critical paths are selected implicitly with the aid of a combination of decision diagrams. An implicit method to eliminate untestable faults along the selected paths is also presented. The effectiveness of the approach is demonstrated on path intensive ISCAS'85, ISCAS'89 and ITC'99 benchmarks.
Cited by 35
Ilia Polian, Christian Miller, P. Engelke et al. · 2008
The academia largely relies on two classes of circuits to benchmark its developments in the field of DFT. The first class are academic benchmarks such as ISCAS-85 [1], ISCAS-89 [2] and ITC-99 [3] circuits. They are reasonably old and thus significantly smaller than today's realistic designs. Furthermore, their characteristics may not match the properties of recent designs. This might facilitate developments which are not useful for current circuits. For instance, ISCAS-85 circuits tend to have many reconvergen- cies and thus a huge number of paths through combinational logic. This triggered adding functionality handling recon- vergencies efficiently to academic test generation tools. This functionality may not be highly relevant in today's practice
Cited by 1
Theodoros Toulas, Spyros Tragoudas · MATEC Web of Conferences · 2016
The multiple transition fault model has been used to represent alternative defective gate combinations in the circuit. However, the number of faults is very large even of modest size circuits and therefore the defective configuration may not be considered. It is shown that multiple transition faults can be stored compactly in Binary Decision Diagrams. Furthermore, important operations for identifying the location of failures are implemented without fault enumeration. Experimental results on some of the largest ISCAS’85, ISCAS’89. and ITC’99 benchmarks demonstrate the scalability of the proposed method.
Cited by 0Open access
M.K. Michael, Stelios Neophytou, Spyros Tragoudas · 2005
The paper shows how to generate a function that contains all possible tests to detect a transition fault. Moreover, a systematic methodology is presented that derives the functions for all transition faults based on only two circuit traversals. Quality tests are generated by requiring that the function formulation considers established sensitization criteria to either activate a transition at the fault site or propagate it to a circuit output. Experimental results on the ISCAS'85 and ISCAS'89 benchmarks demonstrate the promise of the method which can also lead to efficient compaction methods for transition faults.
Cited by 2
Dimitrios Karayiannis, Spyros Tragoudas · 2002
This paper presents a test pattern generator for path delay faults which generates a polynomial number of test patterns that target a large number of functionally sensitizable faults. The number of these faults may be exponential to the input site. Experimental results are presented on the ISCAS'85 benchmarks.
Cited by 4
Rupsa Chakraborty, Dipanwita Roy Chowdhury · 2009
The seed (initial state) of a pseudo-random pattern generator (PRPG) for built-in self-test (BIST), significantly influences the fault coverage and total test application time. This paper introduces a one-pass seed selection algorithm, for any known PRPG. Due to its single-pass nature, unlike the state-of-the-art exhaustive search methods, the proposed algorithm is more time and memory efficient. Experimental results on ISCAS'85 and ISCAS'89 benchmark circuits, and synthetic SoCs built out of the combinational benchmarks, show considerable reduction in test length within comparable fault efficiencies, almost 100%, with respect to the existing methods.
Cited by 7
Mehdi Dehbashi, Görschwin Fey · 2012
Debugging of speed-limiting paths (speed paths) is a key challenge in development of Very-Large-Scale Integrated(VLSI) circuits as timing variations induced by process and environmental effects are increasing. This paper presents an approach to diagnose speed paths under timing variations. First timing behavior of a circuit and corresponding variation models are converted into a functional domain. Then, our automated debugging based on Boolean Satisfiability (SAT) diagnoses speed paths. The experimental results show the effectiveness of our approach on ISCAS'85 and ISCAS'89 benchmarks suites. In average, the diagnosis accuracy of 98:51% is achieved by our approach.
Cited by 5
Ioannis Voyiatzis, Dimitris J. Kavvadias, S. Sinitos et al. · 2015
In this work an algorithm for embedding test sets containing don't care values into sequences generated by binary counters is utilized and evaluated. Furthermore, a simple, yet effective, technique to decrease test application time is explored. Experiments carried out on ISCAS benchmarks reveal that the proposed scheme results in considerably shorter test sequences.
Cited by 0
Charles Gouert, Nektarios Georgios Tsoutsos · 2020
As cloud computing becomes increasingly ubiquitous, protecting the confidentiality of data outsourced to third parties becomes a priority. While encryption is a natural solution to this problem, traditional algorithms may only protect data at rest and in transit, but do not support encrypted processing. In this work we introduce ROMEO, which enables easy-to-use privacy-preserving processing of data in the cloud using homomorphic encryption. ROMEO automatically converts arbitrary programs expressed in Verilog HDL into equivalent homomorphic circuits that are evaluated using encrypted inputs. For our experiments, we employ cryptographic circuits, such as AES, and benchmarks from the ISCAS'85 and ISCAS'89 suites.
Cited by 16
B.S. Greene, S. Mourad, J. El-Ziq · 2002
In this paper we present an efficient algorithm for the selection of flip-flops for partial scan design. The algorithm determines the vertex set to open loops of length K or higher. Applying the algorithm to several ISCAS-89 benchmarks yields the best results for large circuits. Our results consistently indicated it is sufficient to scan a smaller set of flip-flops than the MVFS without significant sacrifice in fault coverage. We have applied the algorithm to RTL benchmarks with promising results.
Cited by 2
D. Ye. Ivanov · The Scientific Issues of Ternopil Volodymyr Hnatiuk National Pedagogical University Series pedagogy · 2008
Under the life cycle of the development of the modern digital circuits a problem of verification of two circuits is arise. It is caused, for example, by using several optimization procedures. In this paper a genetic algorithm of solving this problem is proposed. Reported experimental results on the ISCAS-89 benchmarks confirm the efficient of the proposed algorithm.
Cited by 0Open access
Won Hwa Kim, Hae‐Sim Park, Young-Jin Kim · Electronics Letters · 2009
A simple but effective technique for timing yield enhancement is presented. The proposed technique tunes circuit timing using dual-mode elements, which are special logic gates that can change delay–leakage characteristics at the post-silicon level. In experiments using the ISCAS-85 benchmarks, the proposed technique reduced the timing failure rate by 59.52% on average.
Cited by 1
Gianpiero Cabodi, P. Camurati, Stefano Quer · 2002
Until now, symbolic FSM state space exploration techniques were limited to small circuits. This paper presents a combination of approximate forward and exact backward traversal that handles larger circuits. For the first time, we have been able to generate test patterns for or to tag as undetectable the faults of some ISCAS'89 and MCNC benchmarks never considered before.
Cited by 11
Valeria Bertacco Computer, Valeria Bertacco, Maurizio Damiani et al. · 1997
We present an algorithm for extracting a disjunctive decomposition from the BDD representation of F . The output of the algorithm is a multiple-level netlist exposing the hierarchical decomposition structure of the function. The algorithm has thoretical quadratic complexity in the size of the input BDD. Experimentally, we were able to decompose most synthesis benchmarks in less than one second of CPU time, and to report on the decomposability of several complex ISCAS combinational benchmarks. We found the final netlist to be often close to the output of more complex dedicated optimization tools. 1
Cited by 0
Xinghao Chen, M.L. Bushnell · 2002
We present a generalization of the equivalent search state (EST) approach for test generation. A search state represents the current search status based on prior search decisions. The generalized EST identifies 56% more previously-searched decision spaces than its predecessor on the 1985 ISCAS benchmarks. We present the enabling theorem with a proof, results and an example for sequential circuit test generation.
Cited by 3
Ivask Raik Ubar, E. Ivask, J. Raik et al. · 1998
Current paper presents a test pattern generation approach based on genetic algorithms. The algorithm is designed so that it allows direct comparison with random methods. Experimental results on ISCAS'85 benchmarks [6] show that the proposed algorithm performs significantly better than similar approach published in [1]. In addition, the test sets generated by the algorithm are more compact.
Cited by 0
Rajsekhar Adapa, Spyros Tragoudas · 2008
Existing techniques for path delay fault (PDF) diagnosis do not provide high diagnostic resolution. These techniques fail to prune a large number of fault free candidates from the set of possible candidate faults. This paper presents an efficient technique to prioritize faults (PDFs) among the set of possible candidate faults. A novel approach for PDF prioritization is presented and its effectiveness is demonstrated on the ISCAS benchmarks.
Cited by 2
Rajsekhar Adapa, Spyros Tragoudas · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2009
Existing techniques for path delay fault (PDF) diagnosis prune fault-free candidates using nonfailing patterns but fail to reduce the size of suspect set significantly. This paper presents two alternative techniques that can be applied in a postprocessing manner to further reduce the suspect set by prioritizing paths using only the failing patterns. Experimental results on the ISCAS benchmarks demonstrate that they are time and memory efficient.
Cited by 0
F. Podyablonsky, Nickolay Kascheev · 2010
This paper presents work aimed at developing automatic test pattern generation algorithms and methods based on continuous approach to digital circuits modeling. We explore the idea of solving test search problem by means of continuous optimization. Here we introduce a generalized faulty block model providing a common approach to different fault types modeling at the test pattern generation phase. Presented algorithms and methods are implemented in an ATPG system. We report the experimental results of test pattern generation for stuck-at faults in combinational circuits (ISCAC'85 benchmarks), and also for bridging faults in sequential circuits (ISCAS'89 benchmarks).
Cited by 1