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About 500 papers for “Loop tiling”

Loop Tiling

Jack Dongarra, Piotr Luszczek, Paul Feautrier et al. · 2011

Cited by 0

for loop parallelization and loop tiling

Alain Darte, Georges-andre Silber, Frederic Vivien et al. · 1996

Unité de recherche associée au CNRS n°1398 Combining retiming and scheduling techniques for loop parallelization and loop tiling

Cited by 0

Chapter 10. Loop Tiling

Larkin Ridgway Scott, Terry Clark, Babak Bagheri · Princeton University Press eBooks · 2005

Cited by 0

Revisiting Loop Tiling for Datacenters

Jiacheng Zhao, Huimin Cui, Yalin Zhang et al. · 2018

As DNNs gain popularity in modern datacenters, it becomes imperative to revisit compiler optimizations for DNNs in a colocation scenario. Loop tiling turns out to be the most significant compiler optimization, since DNNs typically apply a series of matrix computations iteratively to a massive amount of data.

Cited by 6

Abstract Tiling Imperfectly-nested Loop Nests

Nawaaz Ahmed, Nikolay Mateev, Keshav Pingali · 2008

Tiling is one of the more important transformations for enhancing locality of reference in programs. Tiling of perfectly-nested loop nests (which are loop nests in which all assignment statements are contained in the innermost loop) is well understood. In practice, most loop nests are imperfectly-nested, so existing compilers heuristically try to find a sequence of transformations that convert such loop nests into perfectly-nested ones but not always succeed. In this paper, we propose a novel approach to tiling imperfectly-nested loop nests. The key idea is to embed the iteration space of every statement in the imperfectly-nested loop nest into a special space called the product space. The set of possible embeddings is constrained so that the resulting product space can be legally tiled. From this set we choose embeddings that enhance data reuse. We evaluate the effectiveness of this approach for dense numerical linear algebra benchmarks, relaxation codes, and the tomcatv code from the SPEC benchmarks. No other single approach in the literature can tile all these codes automatically. 1 Background and Previous Work The memory systems of computers are organized as a hierarchy in which the latency of memory accesses increases by roughly an order of magnitude from one level of the hierarchy to the next. Therefore, a program runs well only if it exhibits enough locality of reference for most of its data accesses to be satisfied by the faster levels of the memory hierarchy. Unfortunately, programs produced by straightforward coding of most algorithms do not exhibit sufficient locality of reference. The numerical linear algebra community has addressed this problem by writing libraries of carefully hand-crafted programs such as the Basic Linear Algebra Subroutines (BLAS) [22] and LAPACK [3] for algorithms of interest to their community. However, these 0This work was supported by NSF grants CCR-9720211, EIA-9726388

Cited by 0

Parametric Tiling of Affine Loop Nests

Sanket Tavarageri, Albert Hartono, Muthu Baskaran et al. · 2010

Abstract. Tiling, a key transformation for optimizing programs, has been widely studied in the literature. Parameterized tiled code is important for auto-tuning systems since they often execute a large number of runs with dynamically varied tile sizes. In this paper, we present a comparative study of three recently developed approaches to parametric tiling of imperfectly nested loops. 1

Cited by 0

Defensive loop tiling for shared cache

Bin Bao, Chen Ding · 2013

Loop tiling is a compiler transformation that tailors an application's working set to fit in a cache hierarchy. On today's multicore processors, part of the hierarchy especially the last level cache (LLC) is shared. The available cache space in shared cache changes depending on co-run applications. Furthermore on machines with an inclusive cache hierarchy, the interference in the shared cache can cause evictions in the private cache, a problem known as the inclusion victims. This paper presents defensive tiling, a set of compiler techniques to estimate the effect of cache sharing and then choose the tile sizes that can provide robust performance in co-run environments. The goal of the transformation is to optimize the use of the cache while at the same time guarding against interference. It is entirely a static technique and does not require program profiling. The paper shows how it can be integrated into a production-quality compiler and evalutes its effect on a set of tililing benchmarks for both program co-run and solo-run performance, using both simulation and testing on real systems.

Cited by 37

Buffered Tiling for Sequences of Loop Nests

Youcef Bouchebaba, Fabien Coelho · 2001

Usually tiling is applied to one loop nest at a time. In this paper we apply tiling and fusion simultaneously to a sequence of parallel nested loops in order to minimize data movements and energy consumption and/or to maximize the speed of execution. Each of these nests uses as input a stencil of data computed in a previous nest. After fusion and tiling, we guarantee that data necessary to the execution of an iteration has been already computed by the previous iterations by delaying the computation of consumer nest. We take into account the relation among the various stencils, the added delays and the tiling parameters and we give a solution for a class of tiling. To store only the live data elements, we compute the surface of these data for every array and during the code generation we replace this array by a buffer whose size is equal to the surface of live data. We measured cache misses for the transformed versions of the example program.

Cited by 0

Generalized full sparse tiling of loop chains

Krieger, Christopher D., author, Strout, Michelle Mills, advisor, Böhm, Wim, committee member et al. · Digital Collections of Colorado (Colorado State University) · 2007

GENERALIZED FULL SPARSE TILING OF LOOP CHAINSComputer and computational scientists are tackling increasingly large and complex problems and are seeking ways of improving the performance of their codes.The key issue faced is how to reach an effective balance between parallelism and locality.In trying to reach this balance, a problem commonly encountered is that of ascertaining the data dependences.Approaches that rely on automatic extraction of data dependences are frequently stymied by complications such as interprocedural and alias analysis.Placing the dependence analysis burden upon the programmer creates a significant barrier to adoption.In this work, we present a new programming abstraction, the loop chain, that specifies a series of loops and the data they access.Given this abstraction, a compiler, inspector, or runtime optimizer can avoid the computationally expensive process of formally determining data dependences, yet still determine beneficial and legal data and iteration reorderings.

Cited by 0Open access

Combining Retiming and Scheduling Techniques for Loop Parallelization and Loop Tiling

Alain Darte, Georges-André Silber, Frédéric Vivien · Parallel Processing Letters · 1997

Tiling is a technique used for exploiting medium-grain parallelism in nested loops. It relies on a first step that detects sets of permutable nested loops. All algorithms developed so far consider the statements of the loop body as a single block, in other words, they are not able to take advantage of the structure of dependences between different statements. In this paper, we overcame this limitation by showing how the structure of the reduced dependence graph can be taken into account for detecting more permutable loops. Our method combines graph retiming techniques and graph scheduling techniques. It can be viewed as an extension of Wolf and Lam's algorithm to the case of loops with multiple statements. Loan independent dependences play a particular role in our study, and we show how the way we handle them can be useful for fine-grain loop parallelization as well.

Cited by 61

Combining retiming and scheduling techniques for loop parallelization and loop tiling.

Laboratoire de l'informatique du parallélisme, Darte, Alain, Silber, Georges-Andre et al. · LARA - Libre Acces aux Rapports scientifiques et techniques · 2006

(eng) Tiling is a technique used for exploiting medium-grain parallelism in nested loops. It relies on a first step that detects sets of permutable nested loops. All algorithms developed so far consider the statements of the loop body as a single block, in other words, they are not able to take advantage of the structure of dependences between different statements. In this report, we overcome this limitation by showing how the structure of the reduced dependence graph can be taken into account for detecting more permutable loops. Our method combines graph retiming techniques and graph scheduling techniques. It can be viewed as an extension of Wolf and Lam's algorithm to the case of loops with multiple statements. Loop independent dependences play a particular role in our study, and we show how the way we handle them can be useful for fine-grain loop parallelization as well.

Cited by 0

Loop Partitioning versus Tiling for Cache-based Multiprocessors

Fabrice Rastello, Fabrice Rastello, Yves Robert et al. · HAL (Le Centre pour la Communication Scientifique Directe) · 1998

In this paper, an efficient algorithm to implement loop partitioning is introduced and evaluated. We improve recent results of Agarwal, Kranz and Natarajan [1] inseveral directions. We give a more accurate estimation of the cumulative footprint, and we derive a much more powerful algorithm to determine the optimal tile shape. We illustrate the superiority of our algorithm on the same examples as in [1] to ensure the fairness of the comparisons.

Cited by 6Open access

Loop Partitioning versus Tiling for Cache-based Multiprocessors

Ecole Normale, Sup Lyon, Fabrice Rastello et al. · 1998

In this paper, an efficient algorithm to implement loop partitioning is introduced and evaluated. We improve recent results of Agarwal, Kranz and Natarajan [1] in several directions. We give a more accurate estimation of the cumulative footprint, and we derive a much more powerful algorithm to determine the optimal tile shape. We illustrate the superiority of our algorithm on the same examples as in [1] to ensure the fairness of the comparisons. Keywords: Compilation technique, hierarchical memory systems, loop partitioning, tiling, cache, data locality, footprint. R'esum'e Nous pr'esentons dans ce papier une heuristique efficace permettant de faire de la distribution de boucles. Nous appuyons notre travail sur un papier r'ecent de Agarwal, Kranz et Natarajan [1] que nous am'eliorons dans de nombreuses directions. Plus pr'ecisement, nous proposons une estimation des empreintes cumul'ees de tuiles plus pr'ecise ; nous proposons une heuristique puissante permettant de minimiser cette e...

Cited by 0

Loop Partitioning versus Tiling for Cache-based Multiprocessors.

Laboratoire de l'informatique du parallélisme, Rastello, Fabrice, Robert, Yves · LARA - Libre Acces aux Rapports scientifiques et techniques · 2006

(eng) In this paper, an efficient algorithm to implement loop partitioning is introduced and evaluated. We improve recent results of Agarwal, Kranz and Natarajan in several directions. We give a more accurate estimation of the cumulative footprint, and we derive a much more powerful algorithm to determine the optimal tile shape. We illustrate the superiority of our algorithm on the same examples as those of Agarwal, Kranz and Natarajan to ensure the fairness of the comparisons.

Cited by 0