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About 3,541 papers for “Vector processor”

Vector processor customization for FFT

Bogdan Spinean, Georgi Kuzmanov, Georgi Gaydadjiev · 2011

Processors and memory systems suffer from a growing performance gap between them. Each technology generation increases the on-chip performance capabilities however, memory bandwidth increases at a much slower pace. Therefore, overall performance improvements are constrained by the available memory bandwidth. In this paper, we address the memory bandwidth problem of vector processors by introducing hardware customizations which drastically reduce the memory transfers required by the FFT computation. We show that an FFT transform of length equal to the machine size Z can be performed using only O(Z) memory accesses, hence we reduce the memory bandwidth requirement by an order of O(log(Z)) compared to a conventional vector machine. We achieve bandwidth reduction by extending a classic IBM S/370 vector architecture for better register re-use. Our hardware extension completely eliminates the input bit reversal phase of the Cooley-Tukey FFT algorithm. Synthesis results suggest that our extension does not impact the machine cycle time and has a small hardware area overhead of the vector register file of under 4.5% while potentially improving vector performance by a factor of 7.5 for Z = 256.

Cited by 3

Fpga-Based Vector Processor For

Algebraic Equation Solvers · 2008

In this paper, a vector unit tightly coupled with a five-stage pipelined scalar processor is designed and implemented on an FPGA platform. This system supports IEEE 754 single-precision floating-point calculations and sparse matrix operations. The W-matrix linear equation solution method for sparse systems is run on this vector processor. The obtained performance demonstrates that large linear algebraic equations, a great challenge to general-purpose processors, can be solved efficiently on our vector processor.

Cited by 0

Optical Linear. Heterodyne Matrix-Vector Processor

E. Pochapsky, David Casasent · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1988

An analog optical matrix-vector processor with 10-bit accuracy is described. The operating mode of the various components of the system and the system architecture are reviewed. The system is capable of handling bipolar and complex-valued data with no loss in throughput. Various applications of this architecture and initial laboratory data and simulation results are provided. Applications addressed include: finite impulse response filters, two high/low accuracy algorithms and systems for solving linear algebraic equations, a correlation cancellation loop processor and new algorithms and architectures for the discrete and continuous steepest descent algorithms and solutions, plus preconditioning algorithms and associated techniques for these systems, and finally constrained LAE solutions for reduced accuracy processors (using ridge regression techniques).

Cited by 3

Implementing the scale vector-thread processor

Ronny Krashinsky, Christopher Batten, Krste Asanović · ACM Transactions on Design Automation of Electronic Systems · 2008

The Scale vector-thread processor is a complexity-effective solution for embedded computing which flexibly supports both vector and highly multithreaded processing. The 7.1-million transistor chip has 16 decoupled execution clusters, vector load and store units, and a nonblocking 32KB cache. An automated and iterative design and verification flow enabled a performance-, power-, and area-efficient implementation with two person-years of development effort. Scale has a core area of 16.6 mm 2 in 180 nm technology, and it consumes 400 mW--1.1 W while running at 260 MHz.

Cited by 8

Modeling mutation and a vector processor

Aditya P. Mathur, E.W. Krauser · 2003

Mutation analysis is a software testing methodology designed to substantiate the correctness of a program Phi . The mutation approach is to induce syntactically correct changes in Phi , thereby creating a set of mutant programs. The goal of a tester is to construct a set of test data T that distinguishes the output of Phi (T) from that of all mutant programs. Test data sensitive enough to distinguish all mutant programs is deemed adequate to infer the probable correctness of Phi . An algorithm is proposed which was designed to exploit the architecture of a vector processor like the Cyber 205 or Cray X/MP. The algorithm manages the simultaneous execution of multiple mutant Fortran 77 programs. This is accomplished by viewing the execution of these mutants as a sequence of vector instructions. The algorithm promises potential to greatly increase the performance of a mutation-based testing system, as well as points towards a general method of simultaneous program execution against multiple data sets.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 16

Modeling mutation on a vector processor

Aditya P. Mathur, E.W. Krauser · 1988

Mutation analysis is a software testing methodology designed to substantiate the correctness of a program P. The mutation approach is to induce syntactically correct changes in P, thereby creating a set of mutant programs. The goal of a tester is to construct a set of test data T that distinguishes the output of P(T) from that of all mutant programs. Test data sensitive enough to distinguish al1 mutant programs is deemed adequate to infer the probable correctness of P.We propose an algorithm designed to exploit the architecture of a vector processor like the Cyber 205 or Cray X/MP. The algorithm manages the simultaneous execution of multiple mutant FORTRAN 77 programs. This is accomplished by viewing the execution of these mutants as a sequence of vector instructions. The algorithm promises potential to greatly increase the performance of a mutation based testing system, as well as points towards a general method of simultaneous program execution against multiple data sets.

Cited by 28

VLSI implementation of a vector quantization processor

Paul Israelsen · 2002

Summary form only given. This presentation contains a discussion of the needs for a hardware Vector Quantization processor and the trade-offs involved in its design and implementation. The Codebook Processor Chip (CPC16) is a VQ processor capable of finding a full-search best match on sixteen codevectors in parallel. Maximum vector size is 625 samples. Full search of larger codebooks is possible by cascading several chips in parallel. Tree search and multi-stage searches are possible by cascading multiple chips in series in a pipeline structure.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cited by 4

Partially Reconfigurable Vector Processor for Embedded Applications

Muhammad Z Hasan, Sotirios G. Ziavras · Journal of Computers · 2007

Embedded systems normally involve a combination of hardware and software resources designed to perform dedicated tasks. Such systems have widely crept into industrial control, automotive, networking, and consumer products. These systems require efficient devices that occupy small area and consume low power. The device area can be minimized by reusing the same hardware for different applications. If possible, reconfiguring the hardware to adapt to the application needs is important for reducing execution time and/or power consumption. Partial reconfiguration facilitates minimum hardware changes to form a new configuration. We have designed a reconfigurable vector processor for embedded applications. Benchmark results on Xilinx FPGAs (Field Programmable Gate Arrays) are presented involving partial reconfiguration for embedded applications that process vectors. Two approaches are studied toward performance evaluation. The first one estimates the required partial reconfiguration time based on the resources consumed by the corresponding vector kernels. The second approach uses the actual measurement of partial reconfiguration time on a platform that supports a particular type of partial reconfiguration. More than 20% performance improvement has been observed for benchmark kernels, without neglecting the reconfiguration overhead. A framework is proposed as well to efficiently manage the reconfiguration overhead for applications involving multiple kernels.

Cited by 0

Compiling for a Heterogeneous Vector Image Processor

Fabien Coelho, François Irigoin · HAL (Le Centre pour la Communication Scientifique Directe) · 2011

Abstract. We present a new compilation strategy, implemented at a small cost, to optimize image applications developed on top of a high level image processing library for an heterogeneous processor with a vector image processing accelerator. The library provides the semantics of the image computations. The pipelined structure of the accelerator allows to compute whole expressions with dozens of elementary image instructions, but is constrained as intermediate image values cannot be extracted. We adapted standard compilation techniques to perform this task automatically. Our strategy is implemented in PIPS, a source-tosource compiler which greatly reduces the development cost as standard phases are reused and parameterized for the target. Experiments were run on the hardware functional simulator. We compile 1217 cases, from elementary tests to full applications. All are optimal but a few which are mostly within a mere accelerator call of optimality. Our contributions include: 1) a general low cost compilation strategy for image processing applications, based on the semantics provided by library calls, which improves locality by an order of magnitude; 2) a specific heuristic to minimize execution time on the target vector accelerator; 3) numerous experiments that show the effectiveness of our strategy. 1

Cited by 2Open access

Accelerator compiler for the VENICE vector processor

Zhiduo Liu, Aaron Severance, Satnam Singh et al. · 2012

This paper describes the compiler design for VENICE, a new soft vector processor (SVP). The compiler is a new back-end target for Microsoft Accelerator, a high-level data parallel library for C++ and C#. This allows us to automatically compile high-level programs into VENICE assembly code, thus avoiding the process of writing assembly code used by previous SVPs. Experimental results show the compiler can generate scalable parallel code with execution times that are comparable to hand-written VENICE assembly code. On data-parallel applications, VENICE at 100MHz on an Altera DE3 platform runs at speeds comparable to one core of a 3.5GHz Intel Xeon W3690 processor, beating it in performance on four of six benchmarks by up to 3.2x.

Cited by 10

VEGAS: Soft Vector Processor with Scratchpad Memory

Christopher H. Chou, Zhiduo Liu, Aaron Severance et al. · 2013

This paper presents VEGAS, a new soft vector architecture, in which the vector processor reads and writes directly to a scratchpad memory instead of a vector register file. The scratchpad memory is a more efficient storage medium than a vector register file, allowing up to 9 × more data elements to fit into on-chip memory. In addition, the use of fracturable ALUs in VEGAS allow efficient processing of bytes, halfwords and words in the same processor instance, providing up to 4 × the operations compared to existing fixedwidth soft vector ALUs. Benchmarks show the new VE-GAS architecture is 10 × to 208 × faster than Nios II and has 1.7 × to 3.1 × better area-delay product than previous vector work, achieving much higher throughput per unit area. To put this performance in perspective, VEGAS is faster than a leading-edge Intel processor at integer matrix multiply. To ease programming effort and provide full debug support, VEGAS uses a C macro API that outputs vector instructions as standard NIOS II/f custom instructions. Categories and Subject Descriptors C.1.2 [Multiple Data Stream Architectures (Multiprocessors)]: Array and vector processors; C.3 [Specialpurpose

Cited by 0

MIMO receiver and decoder using vector processor

B Rajeshwari, K Veena · 2017

The proposed vector processor has single precision floating point adder, floating point multiplier functional units and vector load store unit. The processor consists of five vector registers of 8-words; each word is of 32 bit. It also has 32-bit scalar registers. To increase the performance, pipelining along with vector chaining techniques are implemented. Processor architecture is implemented on ISim simulator using Xilinx. To analyze the performance of the proposed vector processor for number of instructions and speed with respect to scalar processor, 4×4 MIMO Receiver and MIMO Decoder application is demonstrated on the implemented vector processor.

Cited by 2

The triangle processor and normal vector shader

Michael F. Deering, Stephanie Winner, Bic Schediwy et al. · ACM SIGGRAPH Computer Graphics · 1988

Current affordable architectures for high-speed display of shaded 3D objects operate orders of magnitude too slowly. Recent advances in floating point chip technology have outpaced polygon fill time, making the memory access bottleneck between the drawing processor and the frame buffer the most significant factor to be accelerated. Massively parallel VLSI system have the potential to bypass this bottleneck, but to date only at very high cost. We describe a new more affordable VLSI solution. A pipeline of triangle processors rasterizes the geometry, then a further pipeline of shading processors applies Phong shading with multiple light sources. The triangle processor pipeline performs 100 billion additions per second, and the shading pipeline performs two billion multiplies per second. This allows 3D graphics systems to be built capable of displaying more than one million triangles per second. We show the results of an anti-aliasing technique, and discuss extensions to texture mapping, shadows, and environment maps.

Cited by 233