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About 10,000 papers for “Bit array”

Adaptive minimum bit error rate multitarget array algorithm

Yunhui Liu, Yuhang Yang · 2004

The paper proposed a modified least squares despread respread multitarget constant modulus algorithm (LS-DRMTCMA). The cost function of the original algorithm was modified by the minimum bit error rate (MBER) criterion. The novel algorithm tries to optimize weight vectors by directly minimizing bit error rate (BER) of code division multiple access (CDMA) mobile communication system. In order to achieve adaptive update of weight vectors, a stochastic gradient adaptive algorithm was developed by a kernel density estimator of possibility density function based on samples. Simulation results show that the modified algorithm provides remarkable improvements in the BER performance, capacity and near far effect resistance of a given CDMA communication system.

Cited by 4

Reconfigurable Processor Array A Bit Sliced Parallel Computer

Andrew Rushton · CERN Document Server (European Organization for Nuclear Research) · 1986

From the Publisher: Processor arrays have established themselves as an inexpensive form of parallel computer suitable for a wide range of highly parallel applications. They achieve their performance by huge replication of simple processors known as processing elements or PE. This book investigates enhancements to the conventional bit serial PE with the aim of improving its performance in situations where the small grain parallelism of a single instruction-stream, multiple data stream (SIMD) class parallel computer architecture is inefficient. The book describes the development of an SIMD class parallel computer based on processor arrays. Surprisingly, for many problems a large array of bit serial processing elements is a better source of processing power than a small array of complex processors, and the reconfigurable processor array described here is enhanced with floating-point, multiplication, and data cache facilities to improve the operation of such arrays. The RPA also has features that allow clusters of processing elements to operate on each data item so that hardware parallelism can be matched with data parallelism. The implementation of the architecture as a chip design, for possible VLSI realization, is described, and an appendix contains a high level formal description of the processing element in a registertransfer language. Andrew Rushton teaches at the University of Southampton. Reconfigurable Processor Array is included in the series Research Monographs in Parallel and Distributed Computing, copublished with Pitman Publishing.

Cited by 3

Design of Multi-bit Fault Tolerant Array Multiplier

Vishal Verma, Atin Mukherjee · 2024

A multiplier is a major component in digital signal processors (DSP) for performing fast Fourier transform (FFT) and filtering. In this paper, a multi-bit fault tolerant array multiplier has been designed that provides resiliency against various issues that can lead to faults in the system. To design it, we have only used spare adders and multiplexers along with the simple array multiplier. The design incorporates dynamic hardware redundancy, utilizing spare modules to enhance fault detection and tolerance capabilities. Our analysis indicates that the proposed fault tolerant multiplier can effectively tolerate upto three faults simultaneously, thus significantly enhancing the reliability. Our proposed multiplier also offers 40% savings in the area, 45% reduction in power consumption and 18% less delay overhead when compared to the existing fault tolerant multiplier. However, the proposed multiplier is not fully scalable for higher order designs and hardware complexity also increases with the size of the multiplier.

Cited by 0

DFT algorithms for bit-serial GaAs array processor architectures

Gary B. Mcmillan · NASA STI Repository (National Aeronautics and Space Administration)

Systems and Processes Engineering Corporation (SPEC) has developed an innovative array processor architecture for computing Fourier transforms and other commonly used signal processing algorithms. This architecture is designed to extract the highest possible array performance from state-of-the-art GaAs technology. SPEC's architectural design includes a high performance RISC processor implemented in GaAs, along with a Floating Point Coprocessor and a unique Array Communications Coprocessor, also implemented in GaAs technology. Together, these data processors represent the latest in technology, both from an architectural and implementation viewpoint. SPEC has examined numerous algorithms and parallel processing architectures to determine the optimum array processor architecture. SPEC has developed an array processor architecture with integral communications ability to provide maximum node connectivity. The Array Communications Coprocessor embeds communications operations directly in the core of the processor architecture. A Floating Point Coprocessor architecture has been defined that utilizes Bit-Serial arithmetic units, operating at very high frequency, to perform floating point operations. These Bit-Serial devices reduce the device integration level and complexity to a level compatible with state-of-the-art GaAs device technology.

Cited by 0Open access

Implicit Java Array Bounds Checking on 64-bit Architectures

Chris Bentley, Scott A. Watterson, David K. Lowenthal et al. · 2004

Interest in using Java for high-performance parallel computing has increased in recent years. One obstacle that has inhibited Java from widespread acceptance in the scientific community is the language requirement that all array accesses must be checked to ensure they are within bounds. In practice, array bounds checking in scientific applications may increase execution time by more than a factor of 2. Previous research has explored optimizations to statically eliminate bounds checks, but the dynamic nature of many scientific codes makes this difficult or impossible. Our approach is instead to create a new Java implementation that does not generate explicit bounds checks. It instead places arrays inside of Index Confinement Regions (ICRs), which are large, isolated, mostly unmapped virtual memory regions. Any array reference outside of its bounds will cause a protection violation; this provides implicit bounds checking. Our results show that our new Java implementation reduces the overhead of bounds checking from an average of 63 % to an average of 9 % on our benchmarks.

Cited by 0

Circularly Polarized 2 Bit Reconfigurable Beam-Steering Antenna Array

Peiqin Liu, Yue Li, Zhijun Zhang · IEEE Transactions on Antennas and Propagation · 2019

In this communication, a circularly polarized (CP) reconfigurable 2 bit antenna array is proposed for beam-steering applications. The proposed antenna array utilizes a novel CP reconfigurable 2 bit patch antenna as radiation element. For a reconfigurable 2 bit element, there should be four phase states (i.e., 0°, 90°, 180°, and 270°). In the proposed radiation element, a corner truncated microstrip patch antenna is presented for CP radiation. Owing to the symmetry of the patch antenna, the 0° and 180° phase states are achieved by selecting feeding points of the patch instead of using complex feeding network. A 90° digital phase shifter is cascaded to realize the 90° and 270° phase states for the 2 bit reconfigurable element. Based on the novel 2 bit CP element, an eight-element CP reconfigurable 2 bit antenna array is fabricated and tested to verify the design strategy at 3.65 GHz. The measured results match well with simulation. By appropriately controlling the ON and OFF states of p-i-n diodes, the proposed CP array can be steered from -49° to +49°.

Cited by 101

Bit-serial systolic array implementation of a multilayer perceptron

P. J. Murtagh, Ah Chung Tsoi, Neil Bergmann · IEE Proceedings E Computers and Digital Techniques · 1993

The paper describes the implementation of a bit-serial systolic array architecture for a multilayer perceptron. It is shown that both the recall phase and learning phase can be mapped onto a similar systolic array structure, with minor differences. As a result, a combined systolic array structure is proposed for both the recall phase and the learning phase. The design is simulated using the FIRST silicon compiler to solve the exclusive OR problem, and then compared with a 32-bit floating-point simulation. The central element, multiply-and-accumulate operator was fabricated using a 1.2 μm double metal CMOS p-well process by ORBIT semiconductor, and found to perform satisfactorily. The required chips were implemented with the same technology, and performance parameters estimated. Furthermore, the performance of this architecture in solving the NETtalk problem is compared with other implementations.

Cited by 5

A 4-bit array multiplier design by reversible logic

J. Qian · 2015

With the development of mobile computing, the low power design becomes increasingly important in integrated circuits. Thus, more and more concern falls on energy dissipation. However, energy dissipation in irreversible logic design is inevitable, which is explained by Landauer’s principle-kTln2 joules of heat energy will be generated once erasing each bit of information [1]. One of the solutions is designing the circuits by reversible logic.

Cited by 3

A 24 GHz 6-Bit CMOS Phased-Array Receiver

Tiku Yu, Gabriel M. Rebeiz · IEEE Microwave and Wireless Components Letters · 2008

This letter presents a 24 GHz 6 b phased-array receiver implemented in 0.13 mum CMOS. This design is based on a novel active vector generator that results in wideband quasi-quadrature vectors, which are used to synthesize the desired phase response. The active phase shifter has measured rms gain and phase errors of <0.5 dB and < 2.8deg at 23-24.4 GHz, resulting in a 6 b resolution. The phased-array receiver has a gain of 14 dB, a NF of 6 dB, a 3-dB gain bandwidth of 4.7 GHz and wideband input and output match. The chip consumes 30 mA from a 1.5 V supply with dimensions of 0.66 times 1.25 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> including pads (0.5 times 1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> without pads).

Cited by 16

A bit-array representation GA for structural topology optimization

Sheng Yin Wang, Kang Tai · 2003

A bit-array representation method for structural topology optimization using the GA is proposed. The importance of design connectivity is further emphasized and a hierarchical violation penalty method is proposed to penalize the violated constraint functions so that the problem of representation degeneracy can be overcome and the GA search can be driven towards the combination of better structural performance, less unusable material and fewer connected objects in the design domain. An identical initialization method is also proposed to test the performance of the GA operators. With the appropriately selected GA operators, the bit-array representation GA is applied to the structural topology optimization problems of minimum weight. Numerical results demonstrate that the present GA can achieve better accuracy with less computational cost and suggest that the GA performance can be significantly improved by handling the design connectivity properly.

Cited by 7

Design of low leakage SRAM bit-cell and array

Shashank Ranganath, M. S. Bhat, Alden C. Fernandes · 2014

There is an ever increasing need for running various multimedia and computer based applications on a variety of popular digital systems. These applications continue to become increasingly power-hungry and require critical performance levels. To achieve the required benchmark performance, devices have to employ high speed processors in addition to low power on-chip memory. As the power consumed during memory access accounts for a considerable portion of the total power consumption in microprocessors, there is a pressing need to reduce the power requirements of on-chip memory while making sure the data stored in the memory cells remains unchanged. This paper reports design of low leakage Static Random Access Memory (SRAM) Bit-Cell and Array. The SRAM cell and array were designed using 180nm technology and analyzed at 25°C with V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> of 1.8V using Cadence tool. The proposed SRAM cell showed an improvement of around 65% in average SPD over the 6T SRAM cell during the write `1' operation and an improvement of around 66% in average SPD over the 6T SRAM cell during the write `0' operation. Write and Read access times of the proposed 1 kB SRAM Array were recorded to be 27.92% and 25% faster than the 1 kB 6T SRAM Array respectively.

Cited by 4

Transactions Briefs Bit-Level Pipelined Digit-Serial Array Processors

A. Aggoun, M. K. Ibrahim, A. Ashur · 2014

Abstract—A new architecture for high performance digit-serial vector inner product (VIP) which can be pipelined to the bit-level is introduced. The design of the digit-serial vector inner product is based on a new systematic design methodology using radix-2 n arithmetic. The proposed architecture allows a high level of bit-level pipelining to increase the throughput rate with minimum initial delay and minimum area. This will give designers greater flexibility in finding the best tradeoff between hardware cost and throughput rate. It is shown that sub-digit pipelined digit-serial structure can achieve a higher throughput rate with much less area consumption than an equivalent bit-parallel structure. A twin-pipe architecture to double the throughput rate of digit-serial multipliers and consequently that of the digit-serial vector inner product is also presented. The effect of the number of pipelining levels and the twin-pipe architecture on the throughput rate and hardware cost are discussed. A two’s complement digit-serial architecture which can operate on both negative and positive numbers is also presented. I.

Cited by 0

Bit-level systolic array circuit for matrix vector multiplication

J.V. McCanny, J.G. McWhirter · IEE Proceedings G (Electronic Circuits and Systems) · 1983

A bit-level systolic array for computing matrix x vector products is described. The operation is carried out on bit parallel input data words and the basic circuit takes the form of a 1-bit slice. Several bit-slice components must be connected together to form the final result, and the paper outlines two different ways in which this can be done. The basic array also has considerable potential as a stand-alone device, and its use in computing the Walsh-Hadamard transform and discrete Fourier transform operations is briefly discussed.

Cited by 20