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About 10,000 papers for “Bit array”

Bit-Level Parallel Array Algorithms of Vector-Vector and Matrix-Matrix Multiplication

Guo Li, Wang Miao-feng, Tian Qiu et al. · 2006

Based on Horner' rule and Baugh-Wooley algorithm, this paper presents two novel bit-level parallel array algorithms of 2's complement multiplication, and the algorithms have been mapped to systolic arrays by using linear mapping techniques. We propose two efficient systolic arrays of multiply and accumulate (MAC) operation and we also describe the vector-vector and matrix-matrix multiplication that can be efficiently implemented by using the MAC arrays. The two systolic arrays have high performance (low time complexity, space complexity and latency) and consume smaller gate-area in comparison to other architectures. It is suitable for VLSI implementation for its regularity and modularity

Cited by 1

Effect of Two Different Superstrate Layers On Bismuth Titanate (BiT) Array Antennas

Fwen Hoon Wee, F. Malek, Umar Al-Amani Azlan et al. · Scientific Reports · 2014

The microwave industry has shown increasing interest in electronic ceramic material (ECM) due to its advantages, such as light weight, low cost, low loss, and high dielectric strength. In this paper, simple antennas covered by superstrate layers for 2.30 GHz to 2.50 GHz are proposed. The antennas are compact and have the capability of producing high performance in terms of gain, directivity, and radiation efficiency. Bismuth titanate with high dielectric constant of 21, was utilized as the ECM, while the superstrate layers chosen included a split ring resonator and dielectric material. The superstrate layers were designed for some improvement in the performance of directivity, gain, and return loss. The proposed antennas were simulated and fabricated. The results obtained were small antennas that possess high gain and high directivity with 360°, omni-directional signal transmission that resonant types of conventional dipole antenna cannot achieve. The gain of the antenna with the superstrate layer was enhanced by about 1 dBi over the antenna without a superstrate layer at 2.40 GHz.

Cited by 13Open access

Switchable Beamsteering Antenna Array Using 3-bit Phase Quantization at 28 GHz

Md Nazim Uddin, Elias A. Alwan · 2022 IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (AP-S/URSI) · 2022

A novel beam-steerable 3-bit antenna array is presented for millimeter-wave application. The design operates at 28GHz and consists of a tightly stacked aperture feeding antenna with eight reconfigurable quantized phases which can effectively steer the beam from +50º to -50º. Three different configurations were fabricated and tested. The measured antenna is in good agreement with the simulation result. The measured broadside gain was 13.44 dBi with the gain threshold of 10dBi within the steering range (viz. 100º).

Cited by 4

Self-Rectifying Twin-Bit RRAM in 3-D Interweaved Cross-Point Array

Shu-En Chen, Y. L. Chin, Min-Che Hsieh et al. · IEEE Journal of the Electron Devices Society · 2015

A new self-rectifying twin-bit RRAM in a novel 3-D interweaved cross-point array has been proposed and demonstrated in 28-nm high-k metal gate CMOS back end of line (BEOL) process. This high density of array architecture with the cell size only 70 × 100 × 187 nm can be manufactured without additional mask or process. The RRAM film is formed by via plug over shifting between two metal lines in back-end process with TaN/TaO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> N RRAMs on both sides of a single via. The BEOL RRAM shows large read window between states. Fast switching time of 1 us for set operation and 10 us for reset was demonstrated. Excellent selectivity by its asymmetric IV characteristic enables the twin-bit 1R cells to be efficiently stacked in 3-D cross-point arrays without select transistors.

Cited by 1Open access

A compact FPGA implementation of a bit-serial SIMD cellular processor array

Declan Walsh, Piotr Dudek · 2012

An FPGA implementation of a fine grain generalpurpose SIMD processor array is presented. The processor architecture has a compact processing element which is encapsulated into two configurable logic blocks (CLBs) and is then replicated to form an array. A 32 × 32 processing element array is implemented on a low-cost Xilinx XC5VLX50 FPGA using four-neighbour connectivity with the possibility to scale up using a larger FPGA. The processor array operates at a frequency of 150 MHz and executes a peak of 153.6 GOPS (bit-serial operations). Binary and 8-bit greyscale image processing is performed and demonstrated.

Cited by 10

Reservoir computing with two-bit input task using dipole-coupled nanomagnet array

Hikaru Nomura, Kazuki Tsujimoto, Minori Goto et al. · Japanese Journal of Applied Physics · 2019

Abstract Reservoir computing (RC), which utilizes physical phenomena, is a candidate for low energy consumption recurrent neural networks. Recently, we proposed RC which uses a dipole-coupled nanomagnet array as a reservoir, which applies the direction of the static magnetic moment of each nanomagnet as a node state in the array. It is possible to learn binary tasks with one-bit input data using this reservoir. Moreover, more complex tasks such as motion detection utilize multi-bit input data. This study simulates a two-bit binary input RC by employing the dipole coupled nanomagnet array as a reservoir. We apply a binary task with two-bit input data, which requires a memory capacity and non-linear computing capability of the reservoir. Due to the simulations with a macrospin model at a temperature of 0 K, this RC was able to learn these binary tasks by utilizing 24 nanomagnets.

Cited by 13

1-Bit Programmable Circularly Polarized Beam Scanning Array Based on PB Phase

Yajie Mu, Dexiao Xia, Jiaqi Han et al. · 2023

A low-profile 1-bit programmable circularly polarized (CP) beam scanning array based on PB phase is proposed in this paper. The current direction can be changed by regulating the PIN diodes to achieve 0° and 180° phase, i.e. 1-bit. Furthermore, the CP antenna can be rotated in-plane to obtain different initial PB phases. The initial PB phase of each array element is optimized by a genetic algorithm (GA), which effectively eliminates the 1-bit array grating lobe to achieve a single beam scan. The introduction of the PB phase simplifies the way in which the initial phase is fed through the phase shifter. This greatly simplifies the design complexity of the power division and improves the scalability of the array. Simulation results confirm that the proposed 1-bit CP array has no grating lobes and the side lobes are below -10 dB for beam scans of (θ, φ), where φ = [0°,45°, 90°, 135°] and θ = [0°, 15°, -15°, 30°, -30°, 45°, -45°].

Cited by 0

Execution Of Neural Network Algorithms On An Array Of Bit-Serial Processors

B. Svensson, T. Nordström · 1990

Large processor arrays are candidates for performing computations of neural network models at speeds required for real time applications, e.g. in pattern recognition. The paper gives a general model of an array of bit-serial processors and demonstrates the mapping of neural net models on such an array.

Cited by 0

A Single-Channel FMCW Radar Based on 1-bit Time-Modulated Array

Tong Wu, Xinyu Li, Jingfeng Chen et al. · IEEE Transactions on Antennas and Propagation · 2025

In this paper, a single-channel frequency-modulated continuous-wave (FMCW) radar based on 1-bit time modulated array (TMA) is proposed. By utilizing the spectrum folding phenomenon introduced by harmonics de-chirping, the frequency spectrums of beat signals generated by different harmonics are distributed in independent frequency areas, thereby avoiding target ambiguity caused by spectrum crossing and achieving the single-channel estimation of target range, velocity, and direction. The theory of range, velocity, and direction estimation based on multi-harmonic power reconstruction method is established. Meanwhile, the constraint condition among modulation frequency, target range, and target velocity for avoiding target ambiguity is derived. Compared with conventional single-channel FMCW radar based on switched antenna array (SAA) which employs time division multiplexing, the proposed system improves the array reception efficiency significantly by using 1-bit time modulation modules to enable all antenna elements to simultaneously receive echo signals. Moreover, the advantage of the proposed system that the echo signals are received continuously in the time-domain avoids the velocity-direction coupling problem introduced by time-division reception in conventional single-channel system. Hence, the independent detection of range, velocity and direction for high-speed moving targets can be achieved in the proposed system. Numerical simulations are provided to verify the performance of the proposed system, and a C-band eight-element 1-bit TMA is constructed to experimentally verify its feasibility. Simulation results show that compared with the SAA radar, the beat signal power is increased, and the beat frequency estimation error is reduced and the direction-finding accuracy is improved for high-speed targets.

Cited by 0

Design of 4-Bit Array Multiplier Using Multi-wall Carbon Nanotube Interconnects

Debaprasad Das, Sourav Das, Hafizur Rahaman · 2012

In the nanometer regime carbon nanotube has been a potential candidate in replacing the traditional copper based interconnects. The work in this paper analyzes the delay of multi-wall carbon nanotube (MWCNT) based interconnect systems at the system level by implementing a four-bit array multiplier using MWCNT based interconnects. The layout of the multiplier is drawn using MWCNT based interconnects and delay has been analyzed and compared with that of the traditional copper based interconnects. It has been observed that MWCNT based design has 3.4% less delay in the critical path as compared to the copper based design. The paper also describes a methodology of modeling and analyzing a system designed with MWCNT interconnects, using the conventional chip design flow and tools.

Cited by 0

A 6-18GHz 6-bit Phase Shifter for Broadband Phased Array Applications

Hao Zhang, Yuan Wang · 2022 International Conference on Microwave and Millimeter Wave Technology (ICMMT) · 2022

This paper presents a 6-18-GHz 6-bit broadband phase shifter (PS), which includes six stages. In order to acquire high phase shift resolution, broad bandwidth and small chip area, some different structures were used: (1)the switched-transmission-line structure was used to realize 5.625° phase shift. (2)the high-pass/low-pass filter structure was used to realize the 11.25°, 22.5° and 44.5° phase shifts. (3) the magnetically coupled all-pass network structure was used to realize 90° phase shift. (4)the lange-based structure was used to realize 180° phase shift. The phase shifter was designed in a 0.13-μm SiGe BiCMOS technology. The test results show that, the 6-bit phase shifter has a RMS error <4.3° and a insertion loss variation is ± 1dB at 6–18 GHz. The proposed 6-bit phase shifter achieves a high phase resolution with a broad band width. The core die occupies an area of 3.7mm ×1.2mm and consumes only 0.1 mA from a 1.8-V supply.

Cited by 4

1-Bit Circularly Polarized Transmit-Array with Orthogonal Elements in X Band

Silong Chen, Kunping Yang, Zhijing Wu et al. · 2025

In this paper, we present two universal layout schemes for designing a 1-bit circularly polarized (CP) transmit-array utilizing only a single phase-modulated layer. These schemes eliminate the correlation of co- and cross-polarization phase patterns caused by 1-bit phase discreteness in the CP array, effectively preventing cross-polarization beam in the same direction. As a proof of concept, a broadband CP transmit-array antenna with goodish polarization purity beams is designed in X-band around 10 GHz. Compared to a uniform element array, the staggered placement of two orthogonal 1-bit elements significantly improves the cross-polarization discrimination (XPD), achieving a 3 dB axial ratio bandwidth of 32.7%. The performance of wide-angle scanning beams up to 60° further validates the effectiveness. The proposed schemes could be used for CP reconfigurable array antennas, enabling electronic beam-steering with just a single phase-modulated functional layer.

Cited by 0

A W-Band 4-Bit Phase Shifter in Multilayer Scalable Array Systems

Sean Shih, D.-W. Duan, O. Fordham et al. · 2007

This paper presents an ultra-compact W-band 4-bit phase shifter integrated in a 5-layer wafer-scale assembly phased array system. The phase shifter was implemented using a reflective-type circuit topology, consisting of a 3 dB Lange coupler and a pair of reflective loads. GaAs HEMT switches were used for switching the loads to achieve the desired phase shifts. On-wafer measurements of the single-bit test cells show phase deviations of 2.5deg from the target phase shifts and an insertion loss of 1.5 plusmn 0.7 dB at 91.5 GHz, while the measured 4-bit phase shifter data shows an insertion loss of 6.9 plusmn 1.1 dB and better than 10 dB return loss at 94 GHz. With its ultra-compact size, two 4-bit phase shifters can be fit into a 1.6 mm times 1.6 mm array-cell. This phase shifter combines state-of-the-art performance and size. To our knowledge, this is the first reported W-band phase shifter fabricated for multilayer wafer-scale assembly in a phased array system.

Cited by 22Open access

Direction Finding Method in Harmonic Amplitude with One-Bit Time Modulated Array

Zhehan Jing, Xiangtian Meng, Bingxia Cao et al. · 2024

The direction-finding method based on harmonic amplitude is established via a two-element time-modulated array (TMA) system, where the one-bit modulation scheme is utilized to reshape the distribution of the harmonic energy. By using such a scheme, the frequency interval between adjacent harmonics is expanded to the twice of the modulation frequency. The principle of the direction-finding system relies on establishing a mathematical relationship between the ratio of harmonic amplitudes and incident angles. By introducing the time delay in the modulation scheme, the amplitude ratio of harmonics will correspond to two values of incident angle, resulting in the limited scope of angular observation. To address the problem, two sets of relationships between amplitude ratios and angle are introduced to distinguish the ambiguous angle, where the value of the time delay is of importance. Numeric simulation results demonstrate that with a suitable choice of time delay under a one-bit modulated scheme, the direction-finding system can obtain correct estimation results across the full scope of the angle.

Cited by 0

Reduced-Transistor Full Adder Architectures for a PowerEfficient 4-Bit Array Multiplier

Ravi Bolimera, Dayyala Mahesh, Dubbaka Srija Goud et al. · Zenodo (CERN European Organization for Nuclear Research) · 2026

This research uses the Cadence Virtuoso simulation environment and 90nm technology to propose a low-power 4-bit array multiplier with a modified full adder architecture. A typical array multiplier uses 28-transistor full adders to do binary addition in parallel. Nevertheless, this leads to a greater area and increased power dissipation. 22-transistor and 10-transistor full adders are used for parallel binary addition in order to solve this issue. The array multiplier with the 10-transistor full adder design uses less power and provides a better power-delay product than previous full adder designs, according to simulation data.

Cited by 0Open access

Design of 4 GHz 1-bit phase quantized beam steering transmit array

Suresh Kumar, TR, Vinoy, KJ · ePrints@IISc (Indian Institute of Science) · 2019

A 4 GHz transmitarray is designed using 1-bit phase quantized U-slot patch element, which need only two switching elements per unitcell to control the transmission phase. The array consists of 22x14 number of 0.240 size unitcells. Beam scanning from -40° to +40° in the H plane and -20° to +20° is achieved with enhanced gain compared to the feed and SLL is 6 dB below the maximum. Peak gain of 15.3 dBi and SLL of 8.6 dB is observed for broadside radiation. Array is simulated using fullwave solver and radiation pattern results are shown for different scanning angles and frequencies. © 2019 URSI. All rights reserved.

Cited by 0