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About 10,000 papers for “Gate array”
Y. Ikawa, Nagaoki Toyoda, M. Mochisuki et al. · 1984
A 1050-gate GaAs gate array connected as a 6 × 6b parallel multiplier, which exhibits a multiplication time of 10.6ns and 350mW power dissipation, will be covered.
Cited by 7
Julio Dondo · 2016
Cited by 0
Martin H. Weik · 2000
Cited by 9
David Truong, Soe San Win · 2010
Beamforming is an important technique in array signal processing and wireless communication systems. In this project, we investigate the Minimum Variance Distortionless Response (MVDR) beamforming technique and its implementation. The QR-RLS algorithm is chosen because of its advantages of numerical stability and systolic array architecture. The team successfully implemented the real-time beamforming of a linear array with 3 receiving antennas on a Xilinx Virtex-5 FPGA platform. Both the simulation and hardware implementation results are presented in this report.
Cited by 0
Panotopoulos, G., Psaltis, D., An, X. et al. · Infoscience (Ecole Polytechnique Fédérale de Lausanne) · 2000
The Optically Programmable Gate Array (OPGA), an optical version of a conventional FPGA, benefits from a direct parallel interface between an optical memory and a logic circuit. The OPGA utilizes a holographic memory accessed by an array of VCSELs to program its logic. An active pixel sensor array incorporated into the OPGA chip makes it possible to optically address the logic in a very short time allowing for rapid dynamic reconfiguration. Combining spatial and shift multiplexing to store the configuration pages in the memory, the OPGA module can be made compact. The reconfiguration capability of the OPGA can be applied to solve more efficiently problems in pattern recognition and database search.
Cited by 0Open access
Mário Véstias · Advances in information quality and management · 2020
Field-programmable gate arrays (FPGAs) are integrated circuits whose logic and their interconnections are configurable. These devices are field-programmable, that is, they can be configured by the hardware designer without any intervention of the manufacturer. Most FPGAs can be reprogrammed as many times as we want with a vast variety of digital circuits. Some recent FPGA families are system-on-chips (SoC) with one or more microprocessor cores, memory, cache, and reconfigurable logic allowing the implementation of complex hardware/software systems in a single programmable device. This article focuses on the architecture of FPGAs, including the so called SoC FPGA. It explains the main blocks of the FPGA, how they have evolved along the last decades and the perspectives of next generation FPGAs. It also describes some applicability areas and how its architecture have evolved to adapt to some of these target markets.
Cited by 2
J. M. McGrail · Hybrid Circuits · 1988
Software tools are an essential part of any IC design system but there are dangers associated with the introduction of CAD systems. This paper attempts to lift the software cloak which, along with the ubiquitous workstation, tends to cover the finer points of CMOS design. This paper should help to make the designer or user of gate arrays more aware of the important features such as power dissipation, the use of transmission gates, latch-up prevention, the pitfalls of using circuit simulators, and the importance of selecting the correct package.
Cited by 0
Nagaoki Toyoda, Naotaka Uchitomi, Y. Kitaura et al. · 1985
TO INCREASE speed of microelectronic systems, it is the inter-chip signal delay that should be reduced by maximizing the integration level. As the integration level increases, however, the development time becomes longer. The rapid development of LSIs is increasingly important because the product life cycle has been becoming shorter. A
Cited by 11
Robert J. Smith · 1981
Gate array layout is becoming an increasingly important topic in design automation, as utilization of these components expands. In this tutorial a model of gate array physical design is first presented, introducing nomenclature used thereafter. The architecture of a typical gate array layout system is briefly discussed, establishing the environmental setting for more detailed examination of placement and routing techniques.
Cited by 0
X. Hu, Meiyuan Wang, M. Zhang · 2002
BiCMOS gate array circuits and macrocell libraries are designed and fabricated through 2.0 /spl mu/m BiCMOS standard processes. The average gate delay time is as follows: BiCMOS 21 stage inverter, 1.1 ns; BiCMOS 21 stage oscillator, 1.1 ns; BiCMOS 21 stage NAND, 1.3 ns; BiCMOS 21 stage NOR, 1.4 ns. BiCMOS 500 gate array circuits are optimized and 2000 gate array circuits are designed. The delay time of BiCMOS is less than CMOS with large load capacitance.
Cited by 0
Panotopoulos, G., Psaltis, D., An, X. et al. · Infoscience (Ecole Polytechnique Fédérale de Lausanne) · 2000
Cited by 0Open access
George Dekoulis · Directory of Open access Books (OAPEN Foundation) · 2017
This edited volume "Field-Programmable Gate Array" is a collection of reviewed and relevant research chapters, offering a comprehensive overview of recent developments in the field of semiconductors. The book comprises single chapters authored by various researchers and edited by an expert active in the aerospace engineering systems research area. All chapters are complete within themselves but united under a common research study topic. This publication aims at providing a thorough overview of the latest research efforts by international authors and open new possible research paths for further novel developments.
Cited by 0Open access
S. Yano · 1988
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Derrick Chen, Thon F. Knight, Derrick Chen · 1996
Cited by 0
S. Tanaka, Jun Iwamura, J. Ohno et al. · IEEE Journal of Solid-State Circuits · 1984
An 8370-gate CMOS/SOS gate array has been developed using a Si-gate CMOS/SOS process with two-level metallization. The gate lengths of the transistors are 1.8 and 1.9 /spl mu/m for the n-channel and p-channel, respectively. Subnanosecond typical gate delay times have been obtained. Typical delay times of inverter, two-input NAND, and two-input NOR gates are 0.67, 0.87, and 0.99 ns, respectively, under a typical loading condition (three fan outs and 2 mm first metal). It is shown that ECL speed with CMOS power can be achieved in a system by using the CMOS/SOS gate array. Advantages of the SOS device on speed performance are also discussed.
Cited by 16
Achim Hoffmann · 2002
GGADS a general layout system for gate arrays, is presented. The system has been implemented and is capable of designing layouts for configurable gate array master structures. It provides a means for evaluating the suitability of a given master structure for implementing a particular kind of circuit.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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M. Tatsuki, Shigeaki Kato, M. Okabe et al. · IEEE Journal of Solid-State Circuits · 1986
The authors describe an ECL 5000-gate gate array for use in mainframe computers. A modified paired-gate cell is introduced to obtain a high utilization of elements and a high functionality. The appropriate selection of emitter-follower currents is performed to achieve high performance for the LSI. The basic gate delay time is 190 ps/gate at a power dissipation of 2.56 mW/gate by using advanced bipolar transistors. To examine the performance of this gate array, a 16-bit multiplier has been implemented by utilizing the automatic CAD system and mounted on a 148-pin pin-grid array package. The multiplication time is 8.3 ns.
Cited by 13
Jeong-Tyng Li, Malgorzata Marek-Sadowska · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1984
We propose a new approach to the global routing of gate arrays. The method can handle any channel capacities and pin distributions on the chip. The global router first finds unique routes, then pushes connections to the periphery. As outer wiring capacity is consumed, the routing continues inward, connecting pins and making global cell assignments for nets by a centrifugal layering process. The goal is to avoid congestion in the center of the chip, a common problem with conventional methods.
Cited by 45
Psaltis, D., Zhou, G., An, X. et al. · Infoscience (Ecole Polytechnique Fédérale de Lausanne) · 1999
Cited by 0Open access
元嗣 宮野, 13792, 実 渡邊 et al. · 2006
近年，光を用いることで，電気配線では実現不可能な高速な再構成を可能にした光再構成型ゲートアレーが開発されている．しかし，従来の光再構成型ゲートアレーでは再構成速度が16～20 μsであり，FPGA（Field Programmable Gate Array）に比べて高速ではあるものの，実装回路の動作クロックに近い高速再構成は実現されていなかった．また，頻繁な動的再構成に不可欠となる部分的な再構成が考慮されていなかった．我々は，実装回路の動作クロックに近い高速な再構成が可能で，かつ，任意の区画がビット単位で部分再構成可能な差分型光再構成ゲートアレー（ODRGA: Optically Differential Reconfigurable Gate Array）を提案している．本論文では，まずODRGAの概要，及び任意の部分再構成を可能にする差分型光再構成アーキテクチャを示し，高速光再構成を可能にする光再構成アーキテクチャを示す．そして，試作VLSIチップ単体でナノ秒の光再構成が可能であり，パルスレーザダイオードを用いた光学システムでは，システムレベルの光再構成として世界最高速である220 nsでの高速光再構成が可能であることを示す．そして，将来的に，光学部を改良することで，システムレベルでも，ナノ秒の高速光再構成が可能になることを明らかにする．
Cited by 0