Blessil george · 2009
Switch level simulation has become a common means for accurate modeling of MOS circuit behavior. This paper discusses the switch level simulation model as described by [1]. The basic network model and other parameters are thoroughly discussed. Thereafter the paper discusses a new algorithm develop by [2] for detecting logic gate implementation and accurately modeling their switch level behavior. The algorithm has also successfully increased the speed of simulation.
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Resve Saleh, Shyh‐Jye Jou, A. Richard Newton · 1994
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E.-H. Horneber · Fachberichte Simulation · 1985
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Resve Saleh, A. Richard Newton · Kluwer international series in engineering and computer science · 1990
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Randal E. Bryant · Research Showcase @ Carnegie Mellon University (Carnegie Mellon University) · 2018
Data-parallel simulation involves simulating the behavior of a circuit over a number of test sequences simultaneously. Compared to other parallel simulation techniques, data-parallel simulation requires less overhead for synchronization and communication, and it permits higher degrees of parallelism. Two data-parallel versions of the switch-level simulator COSMOS have been implemented. The first runs on conventional machines, exploiting the bit parallelism of machine-level logic operations. This version runs 20-30 times faster than sequential simulation on the same machine. The second runs on a massively parallel SIMD machine, with each processor simulating the circuit behavior for a single test sequence. A simulator running on a 32768-processor machine runs up to 33000 times faster than a sequential simulator on a workstation computer
Cited by 2Open access
Caisso, Jean-Paul, Courtois, B., Informatique et Mathematiques de Grenoble (IMAG), 38 - Saint-Martin-d'Heres (France). Techniques de l'Informatique, des Mathematiques, de la Microelectronique et de la Microscopie Quantitative (TIM3) · OpenGrey (Institut de l'Information Scientifique et Technique) · 1986
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C.A. Ryan, J.G. Tront · 2002
Presents a novel switch level extension to parallel fault simulation and the switch level circuit partitioning needed for parallel processing. Using 9-valued logic, reverse level ordering and a parallel hardware accelerated fault simulator, simulation complexity is reduced to O(L**2), where L is the number of levels of switches encountered when traversing from output to input.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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I.N. Hajj · 2002
A methodology is presented for computing the steady-state solution of switch-level networks. The method is based on a matrix algebra similar in many respects to circuit nodal analysis. The formulation steps are similar to the nodal equation formulation steps and the network matrix has the same dimension and structure as the nodal admittance matrix, except that logic operations (min and max operations) are used in formulating and solving the network equations. Solution algorithms are then developed using the new algebra. The approach has been implemented as a part of a mixed-mode simulator which uses partitioning and sparse matrix solution techniques in analyzing a circuit. In its switch-level mode, the simulator can perform logic and concurrent fault simulation using realistic fault models, including bridging faults, and has been found to be competitive with existing switch-level simulators.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Jain, Alok, Bryant, Randal E. · KiltHub Repository · 1991
In this paper, we present a framework for performing switch-level simulation on hardware accelerators.
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Jain, Alok, Bryant, Randal E. · KiltHub Repository · 1991
In this paper, we present a framework for performing switch-level simulation on hardware accelerators.
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Jain, Alok, Bryant, Randal · KiltHub Repository · 2018
In this paper, we present a framework for performing switch-level simulation on hardware accelerators. A symbolic analyzer preprocesses the MOS network into a functionally equivalent Boolean representation. The analyzer thus converts switch-level simulation into a task of evaluating Boolean expressions. Our approach maps the Boolean representation into the instruction set of the hardware accelerator. The resultant framework supports switch-level simulation on a class of hardware accelerators that traditionally have been limited to gate-level simulation.
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Jain, Alok, Bryant, Randal · KiltHub Repository · 2018
In this paper, we present a framework for performing switch-level simulation on hardware accelerators. A symbolic analyzer preprocesses the MOS network into a functionally equivalent Boolean representation. The analyzer thus converts switch-level simulation into a task of evaluating Boolean expressions. Our approach maps the Boolean representation into the instruction set of the hardware accelerator. The resultant framework supports switch-level simulation on a class of hardware accelerators that traditionally have been limited to gate-level simulation.
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Dan Adler · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1991
A model for MOS transistors that is suitable for logic simulation of VLSI circuits is presented. It is based on the concept of a dynamically directed switch (DDS). As in other switch-level models, the circuit is viewed as a graph whereon transistors are represented by directed edges and circuit nodes are represented by vertices. The problem of finding the steady-state response of the circuit is shown to be reducible to the single-source shortest-path problem in graph theory. A distributed literation process in which each transistor determines its instantaneous direction based on its source and drain vertex labels and updates those labels according to its own resistance is defined. Two types of events in the circuit require the reevaluation of the graph labels: transistors turning on and off. These correspond to edge addition and deletion in the circuit graph. Rather than repeatedly applying a shortest path algorithm to the graph whenever these events occur, the author investigates the possibility of dynamically updating only those labels which were affected by the change. The main result is the development of an algorithm for switch-level simulation based on this incremental-updating technique using only local information. The algorithm is fast and accurate and is extended to deal with timing based on an RC-tree delay model. The implementation of the algorithms presented here within the Lsim mixed-mode analog and digital simulator is described.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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V. Ashok, R. Costello, P. Sadayappan · Proceedings of the 22nd ACM/IEEE conference on Design automation - DAC '85 · 1985
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Chris Chu, Mark Horowitz · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1987
This paper addresses various timing and glitch detection issues in switch-level simulation. Particular attention is focused on charge sharing. We categorize and analyze problems caused by charge sharing. Solutions to these problems are proposed and applied to real designs. Results are reported and compared with SPICE simulation. The computational complexity of our methods is also investigated.
Cited by 52
Yu-an Chen, Vikas Jha, Rajive Bagrodia · 1995
This paper presents the results of an experimental study to evaluate the effectiveness of parallel simulation in reducing the execution time of switch-level models of VLSI circuits. Specific contributions of this paper include: (i)Parallelization of an existing switch-level simulator such that it can be executed with a variety of simulation protocols (almost all previous parallel circuit simulators have focused on gate-level models and have targeted either conservative or optimistic simulators, but not both). (ii) Adapting existing circuit partitioning algorithms designed for gate-level models to switch-level designs and evaluating their effectiveness for parallel simulation. (iii) Demonstrating speedups with both conservative and optimistic simulation protocols for a set of combinational circuits (almost all previous studies on parallel simulation for VLSI circuits have failed to extract speedups with conservative protocols); in particular our experiments showed that it was possible t...
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T. Lee, I.N. Hajj · 2002
The authors describe a method for performing transistor-level logical fault simulation. The method relies on switch-level modeling and uses a switch-level matrix-equation formulation and solution into which fault models are inserted in a straightforward manner. The fault models include transistor stuck-at, node stuck-at, and bridging faults. Both output voltage monitoring and current testing are used for fault detection. The approach has been implemented in a concurrent fault simulator and tested using both combinational and sequential circuit benchmarks. The results of the simulator compare very favourably with existing switch-level fault simulators while allowing more complete transistor-level fault models to be included.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Peter Dahlgren · Chalmers Publication Library (Chalmers University of Technology) · 1995
The presence of realistic faults in CMOS networks, such as shorts and opens, frequently gives rise to intermediate voltage values. At the switch level, these values result in undetermined logic states (X) which are likely to propagate to the outputs, causing uncertainty in the estimation of test set efficiency. The first part of this thesis presents event-driven switch-level algorithms for handling abnormal situations occurring in networks in the presence of faults. A proposal is made for an extension to the traditional single-dominance node model which efficiently solves conflicts that may occur between adjacent nodes assigned the X state and thereby significantly reduces the spread of X values as compared with traditional methods. The degradation of confidence in fault detection measures owing to undetermined output values is discussed. A new switch-level model is presented which allows an arbitrary number of dominant signals associated with the state of a node. The strength of several signal contributions can thereby be taken into account when the logic state is computed. It is shown that the error bounds in the voltage prediction, in many cases, are significantly reduced in comparison with traditional models. An efficient two-pass fault simulation algorithm is presented which, during the first pass, simulates the entire network with a less sophisticated node model and detects any faulty situations in a subnetwork. Second, this subnetwork is evaluated under the proposed multiple-dominance node model. The second part of this thesis deals with the modeling of particle-induced transients in combinational networks and includes results from physical fault injection experiments. A novel technique is presented for determining the relative frequency of Single Event Upsets (SEUs) originating from combinational logic and direct hits in latches. A new switch-level algorithm is proposed for the simulation of transients in combinational networks in which a first-order RC model is applied to the fault injection node for predicting the width of a voltage pulse. The fact that transients may fade out during propagation is efficiently modeled by taking into account the pulse width and the topology of subsequent transistor stages.
Cited by 2
Allen, Jonathan, Rao, Vasant B, Overhauser, David V et al. · CERN Document Server (European Organization for Nuclear Research) · 1988
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Saul Kravitz, Randal E. Bryant, Rob A. Rutenbar · 1989
This work addresses the feasibility of mapping the COSMOS switch-level simulator onto a computer with thousands of simple processors. COSMOS preprocesses transistor networks into Boolean behavioral models, capturing the switch-level behavior of a circuit in a set of Boolean formulas. We describe a class of massively parallel computers and a mapping of COSMOS onto these computers. We discuss the factors affecting the performance of such a massively parallel simulator including: the amount of parallelism in the simulation model, performance measures for massively parallel machines, and the impact of event scheduling on simulator performance. We have developed compilation tools which automatically map a MOS circuit onto a massively parallel computer. Massively parallel switch-level simulation is illustrated by describing our pilot implementation on a 32k processor Thinking Machines Connection Machine System.
Cited by 17Open access