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About 2,771 papers for “interconnect structures”

Chip-last Embedded Interconnect Structures

SMARTech Repository (Georgia Institute of Technology) · 2017

The various embodiments of the present invention provide a novel chip-last embedded structure, wherein an IC is embedded within a one to two metal layer substrate. The various embodiments of the present invention are comparable to other two-dimensional and three-dimensional WLFO packages of the prior art as the embodiments have similar package thicknesses and X-Y form factors, short interconnect lengths, fine-pitch interconnects to chip I/Os, a reduced layer count for re-distribution of chip I/O pads to ball grid arrays (BGA) or land grid arrays (LGA), and improved thermal management options.

Cited by 0

Analysis of VLSI Interconnect Structures

Lawrence Carin, Qiang Xu, Kevin J. Webb et al. · 1987

Theoretical and experimental results are presented for coupled microstrip structures typically used in VLSI, microwave, and millimeter-wave circuits. Full-wave data for pulse and time harmonic propagation is presented. Results from this work can be used in establishing design criteria for high-speed digital circuits.

Cited by 3

Inductance Extraction for General Interconnect Structures

Chun-Ying Lai, Shyh‐Kang Jeng, Yao‐Wen Chang et al. · 2006

As the operation frequency reaches gigahertz in very deep-submicron designs, the effect of on-chip inductance on circuit performance can no longer be neglected. Therefore, it is desired to extract interconnect impedance and inductance accurately. Most previous works on impedance and inductance extraction are based on rectangular discretization which has been shown effective for the classical Manhattan based IC interconnect structures. As technology advances, however, more general IC interconnect structures, such as the X-based interconnect structure, have been in production. Those general interconnect structures allow wires to be routed with non-Manhattan shapes. For the non-Manhattan interconnect structures, rectangular discretization is obviously not sufficient. In this paper, we propose to use the surface integral formulation with triangular discretization to extract impedance and inductance for the general IC interconnect structures. Comparative studies with the well-known FastImp and IE3D show that our approach is flexible and effective.

Cited by 0

On-chip em-sensitive interconnect structures

Dian Li, Malgorzata Marek-Sadowska, Bill Lee · 2010

Due to ever greater current densities in modern IC designs, electromigration (EM) in copper interconnects has become an important reliability factor. In this paper, we analyze current densities on bus and clock networks. We observe that under certain conditions, these networks may become sensitive to EM effects and prone to failure. We perform SPICE simulations on open source Wishbone bus and non-tree clocks for IBM and ISCAS89 benchmarks. Experiments on these networks show that on some wire segments current may flow predominantly in one direction and its density may exceed the maximum allowed values suggested by the International Technology Roadmap for Semiconductors (ITRS). When power network experiences noise, the links of a non-tree clock may carry currents whose densities could be 100 times greater than those of the tree branches. In our study, we compare various methods of reducing the EM effect on interconnects. We demonstrate that in comparison to such design methods as increasing wire widths, reducing circuit frequency or decreasing driver sizes, the technology-based solution of capping copper (Cu) wires with cobalt tungsten phosphide (CoWP) coating works best and eliminates EM violations without area overhead, performance loss or additional design effort.

Cited by 2

Electron tomography of inlaid copper interconnect structures

Heiko Stegmann, Hans‐Jürgen Engelmann, Ehrenfried Zschech · Microscopy and Microanalysis · 2003

Journal Article Electron tomography of inlaid copper interconnect structures Get access Heiko Stegmann, Heiko Stegmann AMD Saxony LLC & Co. KG, Wilschdorfer Landstrasse 101, 01109 Dresden, Germany Search for other works by this author on: Oxford Academic Google Scholar Hans-Jürgen Engelmann, Hans-Jürgen Engelmann AMD Saxony LLC & Co. KG, Wilschdorfer Landstrasse 101, 01109 Dresden, Germany Search for other works by this author on: Oxford Academic Google Scholar Ehrenfried Zschech Ehrenfried Zschech AMD Saxony LLC & Co. KG, Wilschdorfer Landstrasse 101, 01109 Dresden, Germany Search for other works by this author on: Oxford Academic Google Scholar Microscopy and Microanalysis, Volume 9, Issue S03, 1 September 2003, Pages 270–271, https://doi.org/10.1017/S1431927603023286 Published: 05 September 2003

Cited by 2

Stable andCompactInductance Modeling of3-D Interconnect Structures

V. Balakrishnan · 2006

Recent successful techniques fortheefficient simulation oflargescale interconnect modelsrely on thesparsification oftheinverse oftheinductance matrix L.Whilethere areseveral techniques for sparsifying L-', thestability ofthese approximations forgeneral interconnect structures hasnotbeenestablished, i.e., thesparsified reluctance andinductance matrices arenotguaranteed tobe positive-definite. Inthis paper,we present a noveltechnique for reluctance sparsification forgeneral interconnect structures that enjoysseveral advantages: First, theresulting sparseapproximation isguaranteed tobepositive definite. Second, theapproximation is optimal, ina certain well-defined sense.Third, owingtoits computational efficiency andnumerical stability, thealgorithm isapplicable forverylarge problem sizes. Finally ourapproach yields a compactrepresentation ofbothinductance andreluctance matrices forgeneral cases.

Cited by 0

Reliability Test Results for Pt FIB Interconnect Structures

Michael Zaragoza · Proceedings - International Symposium for Testing and Failure Analysis · 1999

Abstract The reliability of FIB deposited Pt structures is assessed through lifetesting of product die and through stress testing of via-intensive test structures. Data is also presented for Pt resistance monitors collected over a 21 month period aimed at assessing the stability of the FIB deposition process. Two product types were subjected to HTOL and HTSS conditions at 125°C followed by temperature cycling. The test structures were stressed at different combinations of temperature ranging from 100°C to 140°C and with currents up to 5 mA. Neither product type experienced any FIB related failures whereas the test structure saw 70% fallout due to degradation of the Pt material within the vias. Temperature cycling did not precipitate any failures. The Pt resistance monitor data showed that film resistance increases with film thickness indicating the incorporation of organic byproducts from the deposition process.

Cited by 1

Interconnect Structures And Methods Of Making The Same

SMARTech Repository (Georgia Institute of Technology) · 2017

The various embodiments of the present invention provide a stress-relieving, second-level interconnect structure that is low-cost and accommodates TCE mismatch between low-TCE packages and PCBs. The various embodiments of the interconnect structure are reworkable and can be scaled to pitches from about 1 millimeter (mm) to about 150 micrometers (μm). The interconnect structure comprises a dielectric body element and at least one interconnection array that provides a conductive path between two electronic components. Each interconnection array comprises a plurality of wires that provide both conductivity and compliance to the overall interconnect structure. The versatility and scalability of the interconnect structure of the present invention make it a desirable structure to utilize in current two-dimensional and ever-evolving three-dimensional IC structures.

Cited by 0

IC test structures for multilayer interconnect stress determination

S. Smee, Michael Gaitan, Donald B. Novotny et al. · IEEE Electron Device Letters · 2000

A new method for measuring strain in multilayer integrated circuit (IC) interconnects is presented. This method utilizes process compatible MEMS-based test structures and is applied to the determination of longitudinal interconnect stress in a standard dual-metal-layer CMOS process. Strain measurements are shown to be consistent for an array of similar test structures. Stress values, calculated from constitutive relations, are in good agreement with published results.

Cited by 16

Manufacturing Methodologies for High Density Interconnect Structures (HDIS)

Kathleen Nargi-Toth, Pradeep Gandhi · Specialized and Legacy Electronics Manufacturing Conferences · 1998

ABSTRACT Supported by strong consumer demand for portability, without compromise to power, accessibility, features or weight, the electronics industry is entering into a new era. This new era is being witnessed at all levels of interconnect technology including, silicon wafer fabrication, PWB manufacturing, shielding for housings, and the cooling methods employed on large chips. In addressing these new requirements, a synergy of manufacturing methodologies is emerging. In silicon chip manufacturing, requirements for metallization of advanced semiconductor interconnections have resulted in a movement towards electroplated metal techniques long known to the PWB manufacturer. In PWB manufacturing, the requirement for finer lines and better utilization of PWB real-estate has given rise to micro via techniques. In concept, the sequential build up (SBU) used on the PWB has a fabrication flow which is not unlike wafer fabrication, where layers of circuitry are added over dielectrics and interlayer connections are made by selective removal of that dielectric from the connection points. For both industries, there is a tremendous learning curve to become efficient with these new manufacturing methods. Even the traditional roles of these two dominant component arms in electronic system evolution are converging. This is most notable in PWB manufacturing. After many years of hearing that future packaging was likely to include laminate based products, the day has finally arrived where there is a significant demand for these small, dense “PWBs”. Traditional PWB laminates such as FR-4 and BT epoxy resins are being used at the platform for these chip scale packages designed with motherboard interfacing styles including PGA, BGA, LGA or SMT mezzanine style connectors. These products are growing in global demand. The market is currently dominated by Japanese producers. A logical domestic source for these laminate based products is the PWB manufacturer. To compete with our Japanese counterparts, new technology will be required. This paper will discuss some manufacturing methods which can be used to produce High Density Interconnection Structures (HDIS) such as the laminate chip carriers and complex PWBs.

Cited by 0