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About 5,100 papers for “test pattern generation”
Procházka, Matěj · Brno University of Technology Digital Library (Brno University of Technology) · 2012
Porozumění významu kalibrace a navržení generátoru kalibrů. Popis jednotlivých kalibrů a jejich použití. Kalibrace frekvence pomocí frekvenčních kalibrů a pravost barvy pomocí barevných kalibrů. Stanovení rozlišovací schopnosti pomocí Faucaultových měrek nebo Siemensovy hvězdy.
Cited by 0
Hašek, Martin · Brno University of Technology Digital Library (Brno University of Technology) · 2010
Tato diplomová práce je zaměřena na vytvoření aplikace, která bude umožňovat simulaci optických vad čoček a také vytvářet testovací vzory. V první části je řešena problematika optických vad čoček a návrh softwarového řešení. Dále pak realizace a implementace jednotlivých modulů v aplikaci. Na závěr je popsáno grafické uživatelské rozhraní a práce s ním.
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Kwang‐Ting Cheng, Li-C. Wang, Huawei Li et al. · 2016
This chapter focuses on automatic test pattern generation (ATPG). Historically, ATPG has focused on a set of faults derived from a gate-level fault model. For a given target fault, ATPG consists of two phases: fault activation and fault propagation. The objective of ATPG is to find an input sequence that, when applied to the circuit, enables testers to distinguish between the correct circuit behavior and the faulty circuit behavior caused by a particular fault. Effectiveness of ATPG is measured by the fault coverage achieved for the fault model and the number of generated vectors, which should be directly proportional to test application time. ATPG efficiency is another important consideration. The chapter describes circuit-based Boolean satisfiability techniques for solving circuit-oriented problems. It presents advanced ATPG research topics, such as for delay faults, crosstalk, and power supply noise. The chapter discusses ATPG for design applications including logic optimization and design verification.
Cited by 0
Cheng, Tim Kwang-Ting, Wang, Li-C, Li, Huawei et al. · Rare & Special e-Zone (The Hong Kong University of Science and Technology) · 2016
This chapter focuses on automatic test pattern generation (ATPG). Historically, ATPG has focused on a set of faults derived from a gate-level fault model. For a given target fault, ATPG consists of two phases: fault activation and fault propagation. The objective of ATPG is to find an input sequence that, when applied to the circuit, enables testers to distinguish between the correct circuit behavior and the faulty circuit behavior caused by a particular fault. Effectiveness of ATPG is measured by the fault coverage achieved for the fault model and the number of generated vectors, which should be directly proportional to test application time. ATPG efficiency is another important consideration. The chapter describes circuit-based Boolean satisfiability techniques for solving circuit-oriented problems. It presents advanced ATPG research topics, such as for delay faults, crosstalk, and power supply noise. The chapter discusses ATPG for design applications including logic optimization and design verification.
Cited by 0
Kwang‐Ting Cheng, Li-C. Wang, Huawei Li et al. · 2016
This chapter focuses on automatic test pattern generation (ATPG). Historically, ATPG has focused on a set of faults derived from a gate-level fault model. For a given target fault, ATPG consists of two phases: fault activation and fault propagation. The objective of ATPG is to find an input sequence that, when applied to the circuit, enables testers to distinguish between the correct circuit behavior and the faulty circuit behavior caused by a particular fault. Effectiveness of ATPG is measured by the fault coverage achieved for the fault model and the number of generated vectors, which should be directly proportional to test application time. ATPG efficiency is another important consideration. The chapter describes circuit-based Boolean satisfiability techniques for solving circuit-oriented problems. It presents advanced ATPG research topics, such as for delay faults, crosstalk, and power supply noise. The chapter discusses ATPG for design applications including logic optimization and design verification.
Cited by 2
Yu Zhang · 2012
In VLSI testing we need Automatic Test Pattern Generator (ATPG) to get input test vectors for Circuit Under Test (CUT). Generated test sets are usually compacted to save test time which is not good for failure diagnosis. Physical defects in circuits are modeled by different Fault Models to facilitate test generation. Stuck-at and transition fault models are widely used because of their practicality. In this work a Diagnostic Automatic Test Pattern Generation (DATPG) system is constructed by adding new algorithmic capabilities to conventional ATPG and fault simulation programs. The DATPG aims to generate tests to distinguish stuck-at fault pairs, i.e., two faults must have different output responses. This will help diagnosis to pin point the failure by narrowing down the fault candidates which may be the reason for this particular failure. Given a fault pair, by modifying circuit netlist a new single fault is modeled. Then we use a conventional ATPG to target that fault. If a test is generated, it is guaranteed to distinguish the fault pair in the original circuit. A fast diagnostic fault simulation algorithm is implemented to find undistinguished fault pairs from a fault list for a given test vector set. To determine the quality of the test vector set
Cited by 0
2006
The complexity of VLSI devices increases rapidly as technology increases, resulting in an increase in the difficulty of test generation. Traditional test generation algorithms target one fault of a fault set at a time to generate a test. This paper presents a brief overview of a few different approaches to concurrent test generation. Concurrent test generation is the process of generating tests by “concurrently” targeting multiple faults.
Cited by 0
Sneh Saurabh · 2023
Chip designing is a complex task that requires an in-depth understanding of VLSI design flow, skills to employ sophisticated design tools, and keeping pace with the bleeding-edge semiconductor technologies. This lucid textbook is focused on fulfilling these requirements for students, as well as a refresher for professionals in the industry. It helps the user develop a holistic view of the design flow through a well-sequenced set of chapters on logic synthesis, verification, physical design, and testing. Illustrations and pictorial representations have been used liberally to simplify the explanation. Additionally, each chapter has a set of activities that can be performed using freely available tools and provide hands-on experience with the design tools. Review questions and problems are given at the end of each chapter to revise the concepts. Recent trends and references are listed at the end of each chapter for further reading.
Cited by 2
Sang‐Hoon Song, L.L. Kinney · 2002
Discusses a test pattern generation (TPG) algorithm for single stuck-at faults in combinational logic circuits. Current TPG systems generate a test vector for fault F/sub i+1/ independently of the computation previously done for faults F/sub 1/, F/sub 2/, . . ., F/sub i/. The algorithm ITPG, generates a test vector for fault F/sub i+1/ by starting with (inheriting) the test vector for fault F/sub i/. A new test vector is generated from inherited values by gradually changing the inherited values. The inherited values may partially activate a fault and propagate the fault signal. Normally, this reduces the number of decision steps and backtracks in the second search. Experimental results for well-known benchmark circuits show that ITPG is very efficient with a small backtrack limit; in combination with other algorithms, it is very efficient for arbitrary backtrack limits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 2
Rolf Drechsler, Görschwin Fey · Lecture notes in computer science · 2006
Cited by 5
Constraint Programming Sebastian, Sebastian Brand · 2007
The problem of automatic test pattern generation for sequential digital circuits is considered from the point of view of constraint programming.
Cited by 0
Xiaoqing Wen, Seongmoon Wang · 2009
Cited by 1
G.E. Taylor, B. R. Bannister, Pam Miller · 1989
Of the four main techniques for the automatic generation of test patterns for digital circuits the authors discuss algebraic techniques. The most widely known algebraic technique is that of Boolean Difference in which boolean functions G(X), F(X) describing the fault free and faulty circuits respectively are produced. A test function T(X) is formed from the exclusive-OR of G(X) and F(X). As an alternative to forming the complete test set and post processing to determine an appropriate test sequence, patterns which test for particular faults may be selected directly from the table. If, for example, a go/no-go test set is required a useful heuristic is to first find a pattern which detects a fault among those with lowest testability. Using either the fault augmented function (via evaluation of a small subset of its truth table) or fault simulation techniques other faults detected by the chosen pattern can be determined and eliminated from the table describing A(X,F). This process is then repeated for one of the remaining faults until a full fault cover has been obtained.
Cited by 0
M. DALPASSO, FAVALLI, Michele, OLIVO, Piero · Institutional Research Information System University of Ferrara (University of Ferrara) · 1995
Cited by 1
Dalpasso Marcello, Favalli Michele, Olivo Piero · Institutional Research Information System University of Ferrara (University of Ferrara) · 1995
So far, the test pattern generation for IDDQ testing has been performed without considering the value of the faulty current in comparison with the minimum current that is detectable as a fault: this approach will be shown to be misleading, since it actually gives optimistic coverage evaluation. Then, this work presents an ATPG strategy that targets the highest values of current during the fault activation, in such a way that either a higher fault coverage can be obtained or a less accurate sensor can be used.
Cited by 0
Wong, Mike Wai-Tak · ePrints Soton (University of Southampton) · 1993
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S. Hillebrecht, M. Kochte, D. Erb et al. · 2015
This article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden.
Cited by 0
Zainalabedin Navabi · 2010
Cited by 2
Laung‐Terng Wang, E.J. McCluskey · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1988
Implementation methods based on cyclic codes are presented for pseudoexhaustive testing of combinational logic networks with restricted output dependency. A modified linear-feedback shift register (LFSR) is used to generate exhaustive test patterns for every output of the circuit. All detectable, combinational faults (those that do not change a combinational circuit to a sequential circuit) in each cone of logic driving a single output are guaranteed to be detected. Examples indicate that LFSRs based on cyclic codes have lower hardware cost and shorter or comparable test lengths than other approaches. These test-pattern generators are well suited to applications where short testing time, low hardware overhead, and 100% single-stuck-at fault coverage are required.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Cited by 66
El-Maidi, Elmostafa · OpenGrey (Institut de l'Information Scientifique et Technique) · 1988
Cited by 0